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TUSB542: What exactly customer should do to perform signal integrity analysis?

Part Number: TUSB542

Hi Team

My customer has following 2 questions. 

Could you kindly help with this? Thanks.

1. The statement in datasheet says, "It is recommended to run an overall system signal integrity analysis, in order to estimate the channel loss and configure the re-driver. "

Customer wonders what exactly he should do to do signal integrity analysis here? 

This is the first time for them to design Type C so they have no much experience. 

It will be appreciate if you could provide material to teach customer how can they do signal integrity analysis. 

2. Table 2 in datasheet shows numbers for EQ, DE and OS. What does the numbers mean in Table 2? 

 Could you give us an example how customer can determine these values? 

Thanks.

Regards,

Jo

  • Hi Jo,

    1. We do not have comprehensive app note here. This analysis is typically done through some simulation software such as Keysight ADS or Allegro. The statement in the data sheet refers to the analyze of the PCB stack and excepted routing of the high speed signal path (trace length, number of vias ,etc.) to estimate insertion loss.

    2. Table 2 show the compensation provided by through receiver equalization and transmitter de-emphasis in dB. From the analysis in (1) you will get some insertion loss estimate in dB for which the high speed signal will need to be compensated. The goal is to keep insertion loss approximately equal to amount of receiver equalization and transmitter de-emphasis provided. 

    Please email internally if you would like more in depth details. Also refer to the FAQ below to get familiar with some terminology.