DS90UB960-Q1: Cant get the pattern generator output working for the 960 deserializer

I have a 960 deserializer connected to an FPGA. I have both port 0 and 1 connected with 4 lanes. I am trying to get the internal pattern gen to work. I have configured it to give a 1080p60 output. I have all 4 lanes of port 0 enabled at 400 Mbps rate. If I look at the FPGA MIPI IP registers I dont see any packets being received. Below is the register writes I am doing to configure the deserializer. Are there any status registers that I can check to see if the port is transmitting? 

Thanks

Jon

struct config_byte_t const deser_patt_cfg[] =
{
	{0x1f, 0x03},			// CSI_PLL_CTL - 800 Mbps
	{0x32, 0x01},			// CSI0 enable
	{0x33, 0x03},			// CSI_CTL - Enable, cont clock, 4 lanes

	{0xB0, 0x00},   		// Indirect Pattern Gen Registers

	{0xB1, 0x01},           // PGEN_CTL
	{0xB2, 0x01},

	{0xB1, 0x02},           // PGEN_CFG
	{0xB2, 0x35},

	{0xB1, 0x03},           // PGEN_CSI_DI
	{0xB2, 0x2b},

	{0xB1, 0x04},           // PGEN_LINE_SIZE1(2400 bytes)
	{0xB2, 0x09},

	{0xB1, 0x05},           // PGEN_LINE_SIZE0 (2400 bytes)
	{0xB2, 0x60},

	{0xB1, 0x06},           // PGEN_BAR_SIZE1 (300 bytes)
	{0xB2, 0x01},

	{0xB1, 0x07},           // PGEN_BAR_SIZE0 (300 bytes)
	{0xB2, 0x2c},

	{0xB1, 0x08},           // PGEN_ACT_LPF1 (1080 lines)
	{0xB2, 0x04},

	{0xB1, 0x09},           // PGEN_ACT_LPF0 (1080 lines)
	{0xB2, 0x38},

	{0xB1, 0x0A},           // PGEN_TOT_LPF1 (1125 lines)
	{0xB2, 0x04},

	{0xB1, 0x0B},           // PGEN_TOT_LPF0 (1125 lines)
	{0xB2, 0x65},

	{0xB1, 0x0C},           // PGEN_LINE_PD1
	{0xB2, 0x06},

	{0xB1, 0x0D},           // PGEN_LINE_PD0
	{0xB2, 0x07},           // 1/60/1080

	{0xB1, 0x0E},           // PGEN_VBP
	{0xB2, 0x24},

	{0xB1, 0x0F},           // PGEN_VFP
	{0xB2, 0x04}
};