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DP83848I: Max Trace length bwtween Phy and Ethernet Jack

Part Number: DP83848I

Dear Sir/Madam,

In my enclosed system design, I can not keep the Ethernet jack connector on board next to PHY IC. So signals between PHY and Jack must pass through connector P/N - 5100147-1 (CPCI J1 connector) and get connected to Ethernet Jack placed on Back plane.

If this topology is acceptable, then what is the maximum trace length between PHY and Ethernet Jack?

If the above topology is not acceptable, then can I place the transformer on board close to PHY IC and as told ethernet jack on back plane? If Ok, the kindly let me know the routing guidelines.

Kindly provide your support.

Regards, 

A Eashwar