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TPS65988: DP Alt Mode Sink gets stuck after sending 4 and 4.8 millisecond HPD pulse

Part Number: TPS65988


CASE 1: Two separate TPS65988DHRSHR chips with port 2 of first chip and port 1 of second chip setup as DisplayPort Sink (GPIO4 HPD input) and Source (GPIO3 HPD output), respectively.
CASE 2: Single TPS65988DHRSHR with port 2 and port 1 setup as DisplayPort Sink (GPIO4 HPD input) and Source (GPIO3 HPD output), respectively.
CASE 3: Single TPS65988DHRSHR with port 2 setup as DisplayPort Sink (GPIO4 HPD input) and single TPS65982ABZQZR setup as DisplayPort Source (GPIO3 HPD output).
CASE 4: Single TPS65982ABZQZR setup as DisplayPort Sink (GPIO4 HPD input) and Single TPS65988DHRSHR with port 1 setup as DisplayPort Source (GPIO3 HPD output).

In each case, the CC bus of the DisplayPort Sink is connected to the DisplayPort Source via USB Type-C in DisplayPort Alternate Mode, while we inject a 4 to 4.8 millisecond HPD pulse into GPIO4 HPD input and look for the same pulse to be echoed by the GPIO3 HPD output. We have found that, in cases 2, 3, & 4, everything works as expected and we see the 4 to 4.8 millisecond HPD pulse echoed at the GPIO3 HPD output. However, in case 1, the TPS65988DHRSHR chip setup as DisplayPort Sink (GPIO4 HPD input) is pulse width sensitive. As long as one does NOT send a HPD with pulse width of 4 to 4.8 millisecond, everything will continue to work as expected, but upon sending a HPD with pulse width 4 to 4.8 milliseconds, the DisplayPort Sink (GPIO4 HPD input) will "get stuck" and will not issue HPDs anymore. The only way to clear this condition is to either do a cycle power or issue a 'GAID' or 'Gaid' 4CC.

  • Hi Mark,

    Thank you for the explanation. 

    Personally, I am not an expert on the DP alternate mode nor the timing requirements for HPD. My expertise is on the Type-C PD communication and the power items related to that. So my question to you is if a 4 to 4.8 millisecond HPD pulse is a valid test? Based on my understanding HPD goes high and remains high until a disconnect. Would you be able to highlight your idea behind the 4 to 4.8 millisecond HPD pulse?

  • Hi Adam,

    Section 4.2.1.3 of the DisplayPort v1.4a Link Compliance Test (r1.0 2020) requires a link training response from a Source DUT in response to a 4 millisecond HPD pulse length. Other lengths are also tested. Note that short (IRQ_HPD) and long HPD pulses are defined. So HPD pulse width matters. 

    Mark 

  • Hi Mark,

    Thanks for the info. Let me look into this item. Will reply to you soon with my thoughts