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DP83848Q-Q1: DP83848Q Validation Questions

t.r.
Prodigy 40 points
Part Number: DP83848Q-Q1

Hi Experts,

My team is new to validating our processor core that uses DP83848Q on analog front end. I have a couple questions:

1. Does the DP83848Q allow for reverse loopback testing in RMII mode? I see the only loopback testing is the internal loopback which is defined as looping the MII signals from RX to TX (and vice versa). Wanted to confirm if this is the same test 

2. Do you have suggestions on validation to ensure we have reliable communication on the cable side? We have had issues in the past with communication dropout on cable side maybe due to cabling. My ideas so far are sending packets in millions (at max IEEE spec packet size) and maxing out the cable length per the datasheet spec. Would like to hear your thoughts on this. 

  • 0
    TI__Mastermind 39795 points

    Hi,

    I will need to talk with the Ethernet team regarding this. I expect a response by the end of the week.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 40 points

    Thank you. Looking forward to hear your feedback soon.

  • 0 in reply to t.r.
    TI__Mastermind 39795 points

    Hi,

    1) Internal loopback is when the data from the TX path on the MII side gets routed to the RX path, essentially testing the MII interface connection only. Reverse loopback, which is described as when data is coming on the MDI side through all the blocks of the PHY and is routed back down just before the MII side internally, is not supported.

    2) Regarding your method to validate the communication on the cable side, that is a great way of checking the communication. You can use a 2 port system, or if you would like to test a single board, you can use a loopback cable as well.

    Hope this helps.

    Sincerely,

    Gerome

  • 0 in reply to Gerome Cacho
    Prodigy 40 points

    Thank you for the answer Gerome.

    If reverse loopback isn’t supported do you have any suggestions on how I can do some sort of loopback testing to validate the MDI side using this PHY?

  • 0 in reply to t.r.
    TI__Mastermind 39795 points

    Hi,

    If you are able to track sent and received data from the MAC, connecting a loopback cable on the MDI side would be able to validate the MDI portion as well as the MII portion of a single board.

    If you have a board that is confirmed to have a working MDI network (another design or one of our compatible EVMs), you could also connect the PHY through the MDI to the working board, and enable BIST on both devices. This would essentially be a two-way BIST checking where PHY A is sending data to PHY B, who is checking that pattern. Meanwhile, PHY B is also sending data to PHY A, who is checking this pattern.

    Sincerely,

    Gerome