SN75DP130: application

Amy

1. Please change the pulldown cap C123 from 1uF to 0.22uF

2. Why do they need R73 and R74? Is it to meet the FPGA common mode voltage requirement?

3. Do they have a DP AUX analyzer to capture the DP link training for each case?

4. Can they also read the DP130 DPCD registers for each case?

Thanks
David

Hi David,

1. The cap C123 has been changed to 0.22uF

2. R69 and R70 resistance have been removed

3. Video output board (DP130) - > video input board (ITE6563+ITE68051)   read AUX data as shown in the table below

a) It is not clear under what circumstances the non-stop read EDID will be triggered;

b) In addition, the video output board FGPA uses the configured parameters to fix the output timing and does not use EDID data. Does DP130 shield the read EDID operation

Hi, 

Can you take a multimeter and measure the AUX common mode voltage on AUXP and AUXN before the AC coupling caps? 

For DP130, the common mode voltage before the AC coupling caps needs to be between 0 and 2V.

If the common mode voltage is in range, the DP130 will just pass through the AUX traffic.

Thanks
David

Hi David,

The voltage about 0.02V.

Best Regards,

Amy Luo

Amy

The schematic seems to be missing from the original thread, can you please attach the schematic and let me double check their AUX connection again?

Thanks

David

Amy

I see R71 (CAD_SNK) is not populated, can they populate R71?

The schematic shows 100k pulldown on AUXP and 100k pullup on AUXN, so I would expect around 3V on AUXN, can they double check the AUXN common mode voltage measurement?

Thanks

David 

Hi David,

R71 is populated according to the reference design.
AUXN voltage is 2.8V.Is there any problem about this voltage?

Amy

Please make sure the CAD_SNK is low. With AUXP around 0V and AUXN around 3V, then I would expect the DP130 passing through the AUX data.

Thanks

David

Hi David,

This is Tess, FAE responsible for the issue related customer. We have confirmed the CAD_SNK is low. 

Below screenshot is the data captured by analyzer. In what condition the Set power state: DOWN will appear? This command will cause training again.  Does there any other influence will be produced by this command? 

Really looking forward to your reply. Thanks.

Best Regards,

Tess Chen

Tess

Can you please send out the full AUX log file? Are they seeing link training failure before the source initiates the Set Power State: DOWN?

From the capture, the DP130 AUX is working properly because it is able to pass the AUX traffic back and forth between the source and the sink, so this question is between the source and the sink implementation.

Thanks

David 

When grabbing the log with a logic analyzer, it is found that there is a problem with reading EDID. Output board card FPGA  ->  DP130  -> Input board card, the output board card are FPGA fixed output timing format according to the upper computer configuration, that is, no need EDID.May DP130 not send the EDID AUX Read command?