DS90UB954-Q1: Pass and Fail Interrupt filtering

Hello,

You are correct that this can be set from registers 0x7C and 0x7D however you also need to ensure that you are setting the ports correctly.  Register 0x0C allows you to select PASS_SEL which is important depending on which port you are reading from.  It is also important when writing to 0x7C and 0x7D to make sure you are writing to the correct register page.  The register page is selected in register 0x4C.  Can you verify that the 0x7C and 0x7D are being set properly by reading back the correct values?

Regards,

Nick

Hi Nicholas,

I am working with David McKinney original poster on this issue.

1) 0x0c = 0x81 (port_0 Rx_enable)

2) 0x4c = 0x01 (port_0 read/write)

Can you give me the settings to implement the following, please?

Pass signal true (high) dependent on a) line count, b) line length, c) parity, & d) 2 previous good frames.  

Pass signal low if/when any of the above criteria is false.

I have already tried many variations on 0x7c and 0x7d.

thanks,

david coburn

Hi David,

Yes I saw David McKinney emailed me yesterday.  Give me a moment to look through the register dump and I will let you know my findings.

Regards,

Nick

Hi Nicholas,

This (Pass/Lock cycling) issue is blocking many other coding efforts as we push to the first Beta release.  Currently we have roughly 2 frame times worth of this cycling.  I believe what I describe above is normal usage for this part, but I have not been able to get it to work.  Please advise on the correct register settings needed for what I described above.

thanks,

david

Nicholas,

Here's a scope capture of what I am talking about...  (Green = lock & Purple = Pass)  You can see that currently Pass is simply tracking Lock..  I would like it to have it's own criteria (obviously still dependent on Lock) and 2 good frames prior to it showing a high = true signal.

thanks,

david

Hello David,

I've looked through the register dump sent to me by David.  What is the value in 0x7D? I know you said that you set it, but in the register dump I received it is set to 0 which would result in the behavior you are seeing.  Can you verify this register setting?

Regards,

Nick

 7A    0   1E   20   DF    1    0   FE   1C   10   7A   7A   81    9    0    0
  0    0    0    0   21    1   61    0    0    0    0    0    0    0    4    2
 20    1    0    0   10    0    0    0    0    0    0    0    0    0    0    0
  0    0    0    3   40    1    F    1    0    0    0    1   14   6F    0   40
  0   E0   71    1    0    0    0    0    0    0    0   12    1   13   CD   64
  0    8    0    3    0    0    0    0   DE    3    0   50   50   D8   8A    0
 68    0    0    0    0   5C   22    0   34    0    0    0    0   7C   10   42
 2B   2C   E4    7   8A    0   30   C5    0    1    A   3C   20    0    0    0
  0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
  0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
  2    F    0    0    8   18    0    0    0    0    0    0    0    0    0    0
  8   14   3F    8   25    0   18    0   FC   33   83   74   80    0    0    0
  0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
  0   43   94    2   60   F2    0    2    0    0    0    0    0    0    0    0
  0    0    0    0    0    0    0    0    0    0    0    0    0    0    0    0
 5F   55   42   39   35   34    0    0    0    0    0    0    0    0    0    

Hi David,

I followed up with the FAE on this and I think he has settings to try.  As for 0x7C I think the default setting for bit 5 is actually a 1.  I will log this to be updated in the future.

Regards,

Nick

Nicholas,

0x3A did separate the Pass signal out from the Lock signal, but it never goes high.  I also tried 0x32, 0x02, 0x01.  All behaved the same.  Lock looks like the first scope capture, but Pass never goes high.

I do not see any CSI errors in the registers, but I do see a link error detect from the 953 in register 0x52 of the 954...  but the main processor says the data is good and I have a good image on the display.

Thoughts?

david

Hi David,

Sounds like some progress at least.  When you say you see errors detected on the 954, are you referring to parity errors?  Can you check what you read in registers 0x55 and 0x56?  If you are receiving parity errors shown in those registers, try increasing the threshold values in registers 0x05 and 0x06.  I think that maybe some errors are being received and that is clearing the PASS signal.

Regards,

Nick

Hi Nicholas,

I was not referring to parity errors, but here's line 0x5n from a dump I just did...

  0    8    0    3    0    0    0    0   DE    3    0   50   50   D8   8A    0

0x55 & 0x56 are both 0x00..

I said address 0x52, but I meant 0x51 when I was talking about the error.  A value of 0x08 here means "Alarm flag for link detect from serializer".  It's saying something is wrong back up at the 953...  

Also, here's line 0x4n from the same dump..

 0   E0   71    1    0    0    0    0    0    0    0   12    1    1    4   64

Look at registers 0x4D & 0x4E.  I see no problems being detected..

Here's 0x0n line to see where my parity error thresholds are at...  I keep them at their defaults...

 7A    0   1E   20   D7    1    0   FE   1C   10   7A   7A   81    9    0    0

david