Hello
Could you review the attached Design file?
Loopback tested under the below conditions.
FPGA High Speed IO Receiver IP : D0_I_PCIEp/N*
FPGA High Speed IO Driver IP : D0_O_PCIEp/N*
VDD_SEL : 1K-GND (3.3V mode)
ENSMB : 1K-GND(Pin-mode)
RATE : Float(Default)
SD_TH : Float(default)
LPBK : 1-GND(INA to OUTB)
EQA1,EQA0 : 20K-GND, 1K-GND
DEMB1,DEMB0 : Float, 20K-GND
But Test Result is PRBS7 Level 0.01~0.02.
We changed the EQA and DEMB, but the test results did not change.
Please Check the loopback test.
Best regards