• State Answer Suggested
  • Locked Locked
  • Replies 7 replies
  • Answers 1 answer
  • Subscribers 34 subscribers
  • Views 814 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCA9306: PCA9036 application question

Max Guan
Intellectual 1350 points

Part Number: PCA9306

Hi team,

Will there be leakage if PCA9306 EN/VREF2 is high while VREF1 is still low?

For example in below schematic, if EN is connected to 3.3V and 3.3V rail goes high earlier than 1.8V rail, will there be leakage from 3.3V to 1.8V?

Thanks

Max

  • 0
    Guru 320170 points

    There must not be a resistor between VREF1 and the power supply. EN and VREF2 must be connected together.

    Even during normal operation, a small current flows into VREF2 and out of VREF1. The only way to prevent this is to pull EN/VREF2 low.

    For slow signals like I²C, there is a simpler circuit: leave VREF1 and VREF2 open, and connect EN directly to 1.8 V. Then the switch is disabled when then 1.8 V supply is off.

  • 0
    TI__Intellectual 1350 points

    Hi Clemens,

    Thank you for your feedback while A question that I notice you mentioned that the current flows from VREF1 into VREF2. While actually the question is if VREF2 and EN goes high earlier while VREF1 keeps low, will there be current flow into VREF1?

  • 0 in reply to Max Guan
    Guru 320170 points

    I did not say "from VREF1 into VREF2". I said "into VREF2 and out of VREF1".

    When the supply connected to VREF2 is powered up first, a current will flow into the supply connected to VREF1.

  • 0 in reply to Clemens Ladisch
    TI__Intellectual 1350 points

    Sorry, to avoid misunderstanding, in normal operation, a small current flows into VREF2 pin from VREF2 supply, and also a small current flows out from supply of VREF1. Is this correct?

    And could you help to explain more about the blocks that you mentioned to leave VREF1 and VREF2 open? Do you mean from schematic design, we could leave VREF1 and VREF2 pin unconnected, and pull-high the I2Cs else where in the schematic?

  • 0 in reply to Max Guan
    Guru 320170 points

    There is a direct connection between VREF2 and VREF1. The 200 kΩ resistor is needed to limit the current. (See the links in [FAQ] How do the LSF translators work?.)

    You always have to pull up the I²C signals to their respective supplies, regardless of whether VREF1/VREF2 are connected or not.

  • 0 in reply to Clemens Ladisch
    TI__Intellectual 1350 points

    Thank you for your comments. I created the reference schematic based on the proposal. Could you help to confirm if the design is OK or we need further modification please?

    And also one more question, customer would like to exchange VREF1 and VREF2 (I2C1/I2C2) routine direction and I think previous discussion indicate it is ok to happen when both VREF1 and VREF2 are 3.3V. We also have a 2nd schematic design as shown below, could you help to review if it is a good one to follow?

    Thank you.

  • 0 in reply to Max Guan
    Guru 320170 points

    Yes, the first schematic is OK.

    The second is not: it would be possible to exchange both sides, but the EN and 200 kΩ connections must always be on the side with the higher voltage.