This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867CR: Network connection issue

Part Number: DP83867CR
Other Parts Discussed in Thread: TIDA-00204

Hello,

We have designed a 6-layer daughter board with DP83867CRRGZ phy where we mount a SOM with a Sitara AM335x and we are experiencing some issues connecting to our local network.

We used 0R series resistors at the RGMII Rx lines as in TIDA-00204 since there is integrated 50-Ω series impedance, the Link LED is on at the RJ45 connector, but we could not see the device, no IP on the network (There are 33R series resistors on the Tx lines at the processor side on SOM). We tried 22R series resistors at the Rx lines and we noticed that we could establish connection sometimes but not always. When it connects it seems that there is no packet drop.

Could that mean there is an impedance mismatch issue on the board? What else would cause such a behavior? Is it possible some kind of startup condition with the reset signal or power to cause this problem?

Some additional info:

-Autoneg Disable = 0 (mode 3) with straps.

-For Stackup and track geometries, values proposed by the manufacturer where used.

-50 Ohm impedance for RGMII signals

-RJ45 with integrated magnetics used.

-All RGMII signals where routed as asymmetric striplines on layer 3 referencing Ground planes on Layers 2 and 5. Layer 4 was not used in the area under the RGMII signals.

-RGMII signals where length matched with lengths between 55 and 58mm for Rx lane and 61-64mm for Tx lane.

 

I am also attaching the schematic with the phy connections and a screenshot of the layout.

 

Thank you very much in advance.

  • Hi Ioannis,

    1. Can you check the internal RX/TX delay settings on the MAC and PHY? Only one of either the MAC or PHY should have internal delay enabled, but not both. I would recommend only enabling internal delay for the PHY.
    2. Can you also try different delay values for RGMII TX/RX? The values can be configured by writing to register 0x0086.

    Regards,

    Adrian Kam

  • Hi Adrian,

    Thank you for the suggestions. I am updating the status after we did some tests with the reset input of the phy because we were suspecting some kind of startup issue.

    We tried different external pullup values (4k7 and 2k7) with no change in behavior so we disconnected it completely from the processor and left it just with the external pullup. Then we noticed that it was working and we could establish connection on every power up, so it seems that internal delay values did not cause the issue.

    Why do you think this would happen? Could it be some kind of undefined state of the reset input or some kind of timing issue that could cause that behavior?

    Regards,

    Ioannis

  • Hi Ioannis,

    It seems it is possible that the internal pull resistors on the processor are causing some issues. The problem might have been alleviated a bit by using the 22 ohm resistors.

    Can you provide the following information:

    1. Can you provide the register values for 0x006E and 0x006F when the processor is disconnected?
    2. Can you provide the register values for 0x006E and 0x006F when the processor is connected and after the PHY is powered-up?
    3. Can you provide an image of the schematic with the strap resistors included?

    Essentially, I would like to take a look at those two registers in the scenarios where you could establish connection and could not establish connection.

    Regards,

    Adrian Kam

  • Hi Adrian,

    Thanks again for your support. I am attaching an image with the strap resistors on the bottom left that where not that visible in the previous one (As a note, just to be sure there is no misunderstanding, the greyed out ones that refer to the RGMII skew, do not exist on the board):

    As for the register values, I am really sorry but at the moment we unfortunately don’t have access to the processor and software so that we can read them. We are trying with my colleagues to find a way to do it and I will share them with you as soon as I have these additional info available.

    It seems it is possible that the internal pull resistors on the processor are causing some issues

    In the meantime, If that is the case, are there any workarounds we can try with some kind of external circuitry (pull-ups, pull-downs e.t.c.) ?

    Regards,

    Ioannis

  • Hi Ioannis,

    In the meantime, can you experiment with different series resistors on the RX lines and see if you can find a value that provides a stable connection?

    I will await for when you can provide me the register information.

    Regards,

    Adrian Kam