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Original question:

DP83869HM: DP83869HM RGMII delay

DP83869HM: RGMII clock shift control issue about ANA_RGMII_DLL_CTRL Register

Yansheng Yue
Intellectual 370 points
Part Number: DP83869HM

Hi.

I was confused about the description of ANA_RGMII_DLL_CTRL Register (address 0x86).

I need to confirm the following questions:

(1) Is the clock-shift value ignored if it is set to aligned mode in RGMII_CTRL Register (Address = 0x32)?

(2) Is it a MUST to set bit[8] to 1 that shift values take into effect? I found it seems that TX-shift value takes into effect only when bit[8] is set to 1.

(3) What is the  meaning of DLL_EN_FORCE_VAL, bit[9] of ANA_RGMII_DLL_CTRL Register? And how to set it?

Thanks.

  • +1
    TI__Expert 5425 points

    Hi Yansheng,

    1. Yes, the clock-shift value is ignored if the device is set to aligned mode in register 0x32.
    2. From our experience, if shift mode in register 0x32 is enabled, then bit[8] does not need to be set in for shift values to take effect
    3. Bit[9] acts as the second step in a two step enable process of setting the shift value. Bit[8] needs to be set, then bit[9] needs to be set for the shift value to take effect. However, as stated in number 2, from our experience, enabling shift mode in register 0x32 should be good. You do not need to configure bit[8] and bit[9] of register 0x86.

    Regards,

    Adrian Kam