DP83822I: Stopped RX_CLK clock for 20us.

Hello,

I am confirming with team if it has something to do with EEE and will get back. Meanwhile can we disable EEE on board A by writting register<0x04D1>[0] =0 and see if you notice any change in behaviour.

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Regards,

Vikram

Hi,  I want to update this phenomena.

Board A is kept power-on and Board B is continued turning Power-ON-OFF repeatedly.  On this condition, RX_CLK on Board A is stopped RX_CLK and keep Low.  (MCU detects stopping clock for 20us.)

This phenomena is occurred under the following condition.

Board A : Fixed 10Mbps Half-Duplex only (Not observed it on Auto-Negotiation mode yet)
Board B : Occur it on both Auto-Negotiation mode and fixed 10Mbps Half-Duplex mode.

After this phenomena is occurred, he requires H/W reset or S/W reset to operate correctly.

On Bootstrap(RX_D1), my customer set "EEE Disable" as the same default.  Also, he confirms default setting at register 0x04D1 and no use of EEE function.

Please let us know the reason.

Thanks and best regards,
M.HATTORI.

Hello,

To confirm, did customer try writting reg<0x04D1>[0] = "0" explicitly other than the required strap setting?

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Regards,

Vikram

Hi, 

>>To confirm, did customer try writing reg<0x04D1>[0] = "0" explicitly other than the required strap setting?

After my customer wrote reg<0x04D1>[0] = "0" and EEE is disabled, he has never occurred the phenomenon stopping RX_CLK.  However he observed RX_DV is kept high.

Could you please let us know the reason why the RX_DV is high?  Also, could you please let us know how to resolve this issue?

Thanks and best regards,
M.HATTORI.

Hello M. Hattori,

Is Rx_DV always high after writting reg<0x04D1>[0]?

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Regards,

Vikram