We are using this retimer to route our DisplayPort signals in to a Kintex 7 FPGA in X-Mode. As specified in the datasheets, we are matching the length of our high speed signals (4 lanes of differential data + 1 differential clock). Our question are:
1. Should we route the CLK signals to have a longer trace length than the DATA lanes so that the clock reaches the FPGA after the data lanes to clock those signals in?
2. If yes, what difference in length should we use between the CLK and DATA lanes?
