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DS90UB954-Q1: how to set pixel clock

Takao Yamamoto5
Expert 1690 points
Part Number: DS90UB954-Q1


Hi team,

You mention 'FPD3_PCLK = 2 × fCLKIN or 1 x fCLKIN' at datasheet p.29.

Could you teach me which should I choose? 

And could you teach the flow to choose?

*Following is copy of datasheet.

Best regards,

Takao

  • 0
    TI__Guru** 112340 points

    Hello Takao,

    this depends on the value of the used External Clock connected to the SER. If the CLK value is between 25-52MHz then you multiply by 2. But if the CLK value is between 50 - 104MHz, then you multiply by 1.

    Please refer to Table 7-6 in the 953 datasheet.