connect FPGA to OLED 12 Bit parallel LVDS and DDR

Jan Bock

Other Parts Discussed in Thread: DS32EL0421

Hello,

my customer is looking for a solution (serializer+ deserializer) to connect an remote OLED Display (12 Bit parallel LVDS, DDR,158 MHz pixel clock, SPI control interface). Neither Display nor FPGA have OpenLDI interface. The distance between FPGA and Display will be 1m in a housing.

Thanks in advance for your suggestions!

Jan

over 4 years ago

0 Ikechukwu Anyiam over 4 years ago

TI__Mastermind 35130 points

Hi Jan,

Sorry but we don't have a solution for serializing/deserializing 12 LVDS lanes.

Regards,

I.K.

0 Jan Bock over 4 years ago in reply to Ikechukwu Anyiam

TI__Expert 3025 points

Hi I.K.

Ikechukwu Anyiam said:
g/deserializing 12 LVDS lanes

did you get me wrong or was that just a typo?

I meant:

12-bit DDR LVDS parallel data interface

something like this:

Regards

Jan

0 Ikechukwu Anyiam over 4 years ago in reply to Jan Bock

TI__Mastermind 35130 points

Hi Jan,

Our terminology is a bit different since most of our SerDes are general purpose, so "12-bit parallel LVDS" sounds like wanting to serialize/deserialize 12 LVDS pairs. So they want to serialize 7 LVDS data lanes + 1 clock, and then deserialize them to LVCMOS (since you mention their display does not have an LVDS interface). Correct?

Regards,

I.K.

0 Matthias Zeilinger over 4 years ago in reply to Ikechukwu Anyiam

Prodigy 110 points

Hi I.K.,

you are right. The interface consists of 12 LVDS pairs and one clock. The transmission mode is DDR at 158 MHz. Since the source is an FPGA, 24 bit with 316 MHz can also be output.

+1 Ikechukwu Anyiam over 4 years ago in reply to Matthias Zeilinger

TI__Mastermind 35130 points

Hi Matthias,

To be clear you are in fact looking to serialize/deserialize 12 LVDS data lanes + 1 LVDS clock lane? Unfortunately we do not have a solution for this. The most we have is 5 + 1 clock with the DS32EL0421.

Regards,

I.K.

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connect FPGA to OLED 12 Bit parallel LVDS and DDR