Hi Team,
From a signal standpoint on RIN[1:0], what is the criteria that will lead to loss of LOCK at the 948? I believe the signal at RIN[1:0] needs to be correct and stable, but is this defined by timing parameters? I see Figure 6-7 in the datasheet provide some indication of specification for RIN[1:0], but that does not provide a sense of timing. Basically, when the FPD-Link signal is received by the CDR block, what is the CDR block looking at to determine that LOCK has been established or lost?
If there is a disturbance on RIN[1:0] (for example, loose connection, EMC, too much jitter, voltage spike), is it possible that the disturbance could be so quick that the CDR block doesn't register it and maintains LOCK? Or is the CDR block super sensitive, so any deviation from a correct and stable signal will result in loss of LOCK?
Thank you!
Jared
