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DS90UB933-Q1: tCLKT spec question

Yuta Kurimoto
Genius 10600 points
Part Number: DS90UB933-Q1

Hello Team,

Thanks for your support.

Customer input PCLK=72MHz for the PCLK pin. However their clock signal is large jitter. So they plan to add damping resistor for PCLK line in order to suppress the clock jitter.

But as a conflict, the damping resistor make slower slew rate. Now they can't meet the tCLKT spec in the datasheet.

Q. What problem will happen if they exceed the tCLKT(max) spec?

Q. The tCLKT is specified in the condition of 50MHz-100MHz. If the PCLK range become narrow, can the tCLKT spec be more relaxed?

Thanks,

Yuta Kurimoto

  • 0
    TI__Mastermind 18755 points

    Hello Yuta,

    Unfortunately we test these parts under very specific conditions.  If the spec in the datasheet cannot be met then we will not be able to guarantee proper operation of the part.

    Regards,

    Nick

  • 0 in reply to Nicholas Darash
    TI__Genius 10600 points

    Hello Nick,

    In my understanding, essentially we need to satisfy the T(TCHI), T(TCIL) specs. but I'm not sure why we also need to satisfy the slew rate spec t(CLKT). I know we can't guarantee any behavior when exceeding the recommended operating condition. But I want to know the potential risk when exceeding tCLKT(max). Do you have any idea about what happen when exceeding tCLKT(max)?

    Or is the tCLKT spec just derived from a half value of T(TCHI), T(TCIL)?

    Thanks,

    Yuta Kurimoto

  • +1 in reply to Yuta Kurimoto
    TI__Mastermind 18755 points

    Hello Yuta,

    A lot of internal timing is dependent on the PCLK.  Depending on what mode the device is operating in, the forward channel may be derived from the PCLK.  If a valid PCLK  cannot be received by the 933 then it will not be able to receive the data from the imager, it will revert back to using the internal VCO and so on.  I can't say exactly when it will fail but I would recommend that you do not exceed the maximum timing on the PCLK signal.

    Regards,

    Nick