DP83869HM: POR Timing

Hello,

We are looking into this issue and will provide feedback by Thursday of this week.

Thank you,

Nikhil

Nikhil,

Please advise.

Hello,

Sorry for the delay. Can you provide a scope capture of the supply and clock ramp? 

Thank you,

Nikhil

Supply Ramp

• Ch1 = VDDA2P5
• Ch2 = VDDIO
• Ch3 = VDDA1P1
• Ch4 = VDDA1P8

Clock Out Timing

• Ch3 = VDDA2P5
• Ch2 = VDDIO
• Ch1 = CLK_OUT

Clock Timing

• Ch1 = VDDA2P5
• Ch2 = VDDIO
• Ch4 = XI

Real Clock Frequency

• Clock frequency looks correct despite incorrect looking frequency during POR; likely due to scope setting in measurement or POR timing.

Reset

• Ch1 = VDDA2P5
• Ch2 = VDDIO
• Ch3 = RESET_N (APP_RESET)

Hello,

Thank you for providing the detailed scope plots. Based on the second capture, it looks like the clock is coming up after the supplies are already ramped. To ensure the device does not latch onto any noise as a possible clock source, it would be best to hold the device in reset until all supplies and clock are ramped, rather than initiate the reset after system has booted. Based on the last plot, it looks like the reset signal is held at an intermediate level (looks like 1V). Is it possible to force reset all the way low during power-on?

Thank you,

Nikhil

Hi,

In our original design we have a 1k pulldown on the reset line, but it's not strong enough to combat the internal pullup of the phy reset. This causes the voltage to hang ~1.1v until our FPGA (used to control the reset line) is loaded about 600ms after power-on (this is when the reset line goes to 3.3v in the 5th image above). The FPGA does an additional reset pulse after it's been loaded.

Is it required to meet the initial POR reset timing in order to guarantee a fully functional device, or is a hard reset sometime later good enough?

We can get the chip working by toggling the reset line after power-up, but sometimes following a reset pulse the phy gets into a state where it doesn't respond on the MDIO bus (on any address). If this happens, another reset pulse will usually bring it back. Our work-around so far has been to just pulse the reset until the phy comes up as expected.

Thanks.

Hi Dylan,

Would a stronger pull-down allow the voltage to reach the VIL limit? What is the VDDIO level used? If VDDIO = 3.3V, the MAX VIL limit should be 0.8V. 

A hard reset after supplies are stable may be ok, but as mentioned, to ensure the device does not latch onto any noise as a possible clock source, it would be best to hold the device in reset until all supplies and clock are ramped, rather than initiate the reset after system has booted. Is it possible to hold reset low until supplies are stable?

Thank you,

Nikhil

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

Our issue was including an unnecessary capacitor on the oscillator input. We removed it to have the oscillator going directly into the phy and the reset issues we were seeing went away.

Thanks for the help.