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The delay value of this device is higher than the theoretical value

kaichuan cao
Prodigy 60 points

SN65LBC173ADR chip for high and low level conversion delay description

Project background

schematic diagram

It can be seen from the chip design documents that the maximum delay of high-low level conversion is 16ns, generally 12ns, and the delay time measured by oscilloscope is 24ns. The test diagram is shown in the figure below. How to solve this problem? How to optimize the circuit is needed to reduce the delay value to the normal range.

  • 0
    TI__Mastermind 25705 points

    Unfortunately this kind of timing parameter is tricky to measure. You have to follow exactly the test setup in the datasheet to get the same result. The difference I can think of (I'm sorry the pictures are too small to see the detail) is 1) input signal needs to be 0V to 3V; 2) the output mark is at 1.5V (not half Vcc). If the observation is correct, the customer can consider using 3.3V logic input with 5V supply.

  • 0 in reply to Hao L
    Prodigy 60 points

    Thank you very much for answering my question，No matter how  test it，The test value is always greater than the typical value，Even beyond the maximum.According to your suggestion， input signal mark is at 1.5V,the output mark is at 1.5V，The test value is still 24ns.I really want to know why？Or, please give me your test report.

    t can be seen from the figure that the test value is much larger than the typical value.I look forward to your satisfactory reply

  • 0 in reply to kaichuan cao
    TI__Mastermind 25705 points

    Two more places you could check: 1) if the load is 15pF (or you could test with the output open); 2) fix one side of the input to 1.5V.

    As I checked the device's test data, the mean is about 12ns and min and max is around 11ns and 13ns. One sigma is less than 0.5ns. I'm sorry  the data is prohibited to post on a public forum. 

  • 0 in reply to Hao L
    Prodigy 60 points

    Thank you very much for answering my question，According to your suggestion.

    First，I test Output with load ，As shown in the figure below，The test value is still greater than the typical value，All above 24ns.

    Second，I test with the output open and fix one side of the input to 1.5V,As shown in the figure below，Since A is always higher than B, soChange the fixed input side to 2.5V

    Last，I test with the output open and fix one side of the input to 2.5V,As shown in the figure below，The test value is still greater than the typical value，All above 24ns.Even beyond 30ns.

    I really want to know what defects in my design cause the delay value to be too large,If you can send your test value to my email, I will be very grateful. My email is caokaichuan@crprobot.com ，I look forward to your reply.

  • 0 in reply to Hao L
    Prodigy 60 points

    I think I've found the problem，I used two types of chips（15M21LB4-65LBC173A and 69AJ56M-65LBC173A），As shown in the figure below

    15M21LB4-65LBC173A

    The delay value of this chip is abnormal.

    691J56M-65LBC173A

    The delay value of this chip is normal.

    The two chips have the same model but different performance. Is it because of different production places or other reasons？

  • 0 in reply to kaichuan cao
    TI__Mastermind 25705 points

    Can you advise where you purchased the parts? I'm checking the manufacture data for you.

  • 0 in reply to Hao L
    TI__Mastermind 25705 points

    I have confirmed that 691J56M is TI part. With your confirmation of the purchase channel, I will send the follow up instruction to caokaichuan@crprobot.com.