SN65DSI83: Schematic review

Hi Navin,

Have you checked that this device has enough throughput to support only 2 DSI data lanes? Please reference this FAQ: https://e2e.ti.com/support/interface/f/interface-forum/945185/faq-sn65dsi84-sn65dsi83-sn65dsi84-and-sn65dsi85-resolution-guide 

I also recommend adding a placement for an external REFCLK for debug purposes (you can just leave it unpopulated in the BOM).

Regards,

I.K. 

Hi IK

Thanks for your reply. I had a look the FAQ link that you sent

Max 50MHz (typ 33.3MHz)

Using 16bpp

DSI CLK = LVDSCLK*bpp/(2x#DSILanes)

DSI CLK = 50*16/4 = 200MHz

Hi IK

Sorry, pressed send before I finished the last post,

I was wondering if above calculations are correct? My LVDS screen max clock frequency is 50MHz and we are using 16bpp for now.

For debug external REFCLK can I use the CDCEL913PW exactly as shown in the EVK? 

Otherwise, is the rest of the circuit ok?

Thanks in advance

Navin

Hi IK

Thank you very much for verifying schematic and confirming CDCEL913PW. I will pass on this information to my software team, regarding 16bpp not being supported by SN65DSI83.

Thanks
Navin