From Figure 1 of the DS, it looks like XI clock needs to be running before device powers-up, but I can't find a mention of this in the DS.
What kind of timing requirements does the XI clock on power-up/reset?
Consider the following application conditions:
- 2-supply configuration
- XI pin's CLK is 1.8V signal
- In a customer design, VDDA2P5, VDDIO, VDD1P0 are all stable before the CLK is supplied
Is there any issue with the above? (Appreciate any supporting evidence / info if this is acceptable)
Regards,
Darren