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SN65LV1224B: DS92LV1212A Lock condition

Kazuhiko Hirano
Genius 15118 points
Part Number: SN65LV1224B

Hello,

 

My customer replaced DS92LV1212A by SN65LV1224B, then facing a false lock issue with 10 to 30% possibility.

 

They are looking into what could make the diffrences.

First of all, they would like to confirm if Lock condition for both devices are exactly identical or not.

SN65LV1224B datasheet states “The deserializer does not go into lock until it finds a unique four consecutive cycles of data boundary (stop/start bits) at the same position.” So, it is clear at least four consecutive low to high transition in the same position is required to make LOCK_ low.

However, looking at DS92LV1212A datasheet, it just say “This occurs when more than one Low-High transition takes place in a clock cycle over multiple cycles.” and it is unclear exactly how many consecutive low to high transition in the same position is required to make LOCK_ low.

 

Please let me know the exact DS92LV1212A lock condition.

 

Best regards,

 

K.Hirano

Hello,

 

My customer replaced DS92LV1212A by SN65LV1224B, then facing a false lock issue with 10 to 30% possibility.

 

They are looking into what could make the differences.

First of all, they would like to confirm if Lock condition for both devices are exactly identical or not.

SN65LV1224B datasheet states “The deserializer does not go into lock until it finds a unique four consecutive cycles of data boundary (stop/start bits) at the same position.” So, it is clear at least four consecutive low to high transition in the same position is required to make LOCK_ low.

However, looking at DS92LV1212A datasheet, it just say “This occurs when more than one Low-High transition takes place in a clock cycle over multiple cycles.” and it is unclear exactly how many consecutive low to high transition in the same position is required to make LOCK_ low.

 

Please let me know the exact DS92LV1212A lock condition.

 

Best regards,

 

K.Hirano

  • 0
    TI__Mastermind 35130 points

    Hi Hirano-san,

    These are different devices so the lock conditions are not the same. The lock conditions of the DS92LV1212A are described in the "Initialization" section in the datasheet and illustrated in Figure 7.

    Did the customer reference this application note when switching to SN65LV1224B? https://www.ti.com/lit/an/slla435/slla435.pdf 

    There is an important difference described in this document: "However, the tolerance spec on the REFCLK frequency for SN65LV1224B is much tighter than it is for DS92LV1212A and DS92LV1224. This may be significant for some applications. If an existing application using the DS92LV1212A or DS92LV1224 uses a REFCLK that is not within ±100 ppm of the operating transmission frequency (determined by TCLK on the serializer), then it is not possible to swap the DS92LV1212A or DS92LV1224 with the SN65LV1224B without changes to the design."

    This could explain the locking issues they are seeing with SN65LV1224B. 

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    TI__Genius 15118 points

    I.K.,

     

    Thank you for your response.

     

    My customer referenced the app note and reference frequency and accuracy should not be a problem.

    They are using unique sync data stream after powerup at their design, had not seen any issues with it and had 100% established proper synchronization with DS92LV1224. 

    However, by replacing DS92LV1224 by SN65LV1224B, they are seeing the false lock with 10 to 30% possibility.

     

    They are now looking into their data stream and looking for a specific data pattern, RTM, for SN65LV1224B.

    But they would also like to know what the RTM is for DS92LV1224 to confirm a reason why DS92LV1224 works fine.

    DS92LV1224 datasheet figure 7 does not provide useful information about the RTM.

    So, please let my customer know specifically how many clock cycle of the same location rising edges could be a RTM for DS92LV1224.

     

    Best regards,

     

    K.Hirano

  • 0 in reply to Kazuhiko Hirano
    TI__Mastermind 35130 points

    Hi Hirano,

    From the description in the datasheet it doesn't look like there is an "exact" lock condition for random data. An RTM lock could potentially happen in 1-2 clock cycles depending on the "false lock" circuitry. 

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    TI__Genius 15118 points

    I.K.,

     

    Since only SN65LV1224B sometimes gest false LOCK, I expected DS92LV1212A needs more than or equal to five rising edges at the same position to get the false LOCK.

    Are you sure that DS92LV1212A could LOCK with just 1-2 clock cycles? If so, it is against what my customer is observing, though.

     

    Best regards,

     

    K.Hirano

  • 0 in reply to Kazuhiko Hirano
    TI__Mastermind 35130 points

    Hi Hirano,

    That's my understanding from the datasheet. It doesn't look like there is a quantifiable number of clock edges or else it would be listed in the datasheet. Unfortunately I don't have any further information about it.

    Regards,

    I.K.

  • 0 in reply to Ikechukwu Anyiam
    TI__Genius 15118 points

    I.K.,

     

    Looking at the received data stream when the false lock occurs, SN65LV1224B falsely recognizes b8 to b9 as Start to Stop.
    Please see the following data patterns my customer is using.
    tidrive.itg.ti.com/.../dbb8a018-179b-4de2-8b2f-e58a9433ec19

    In their data pattern, b8=1 and b9=0 repeats every other TCLK cycle (TCLK=33MHz on their app)The RCLK output is 33MHz when the false lock occurs, but SN65LV1224B falsely recognizes b8 to b9 as Start to Stop even if b8 to b9 rising edge cycle is 16.5MHz.
    This false lock has never happened with DSLV1212A on the app so far.
    I guess it relates to the difference between the two devices, Clock frequency is 10 to 66MHz at SN65LV1224B, but it is 16 to 40MHz at DSLV1212A.

    They tried the modified data pattern that does not include “1” to “0” every cycle or every other cycle, then the false lock disappeared.

    My customer would like to hear TI official comments about the root cause of this issue and confirm if their workaround is firm to resolve the issue.

    Best regards,

    K.Hirano

  • 0 in reply to Kazuhiko Hirano
    TI__Mastermind 35130 points

    Hi Hirano,

    I found this post from some years ago and I believe it addresses the customer's issue: https://e2e.ti.com/support/interface/f/interface-forum/228343/sn65lv1224b-does-not-lock/812802#812802 

    It looks like the multiple 10 was causing the device to falsely lock.

    Regards,

    I.K.