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TFP401PZPEVM: TFP401APZP DCLK issue

Part Number: TFP401PZPEVM
Other Parts Discussed in Thread: TFP401, TFP403

Hello 

I can display the image on the display module. But there is fixed horizontal noise.
I trying to measure the DCLK signal and found that this signal become a sin waveform not square waveform.
May I ask if anyone can help to provide advice or what could be causing this

The waveform link: https://drive.google.com/file/d/1lygIBQUH45WfLJ5rGz367oD8_h7NTXqf/view?usp=sharing
The video link: https://drive.google.com/file/d/148VMnPo9WhM1YFBKCuPOpO2rmyOpkWH6/view?usp=sharing

Much thanks,

Simon

  • Hi Simon,

    That's a very small display. What clock frequency is the display expecting? Have you checked that it's within the TFP401's support frequency range?

    Regards,

    I.K. 

  • Hello I.K.:

    Yes, the display is around 0.7 inch which is Micro OLED display.

    My display module's resolution is 1280x1024 @ 60HZ. I'm not sure the TFP401 can or not support this display.

    But it can display the image and video on it, I think it should be work.
    Here is my schematic:https://drive.google.com/file/d/1UrLBNVL92RsSIxg5RVkZTGvqIGDyWJYd/view?usp=sharing
    Would you please help me to confirm it? 
    Do I make something wrong?
    Much thanks for your kindly support.

    Simon 

  • Hi Simon,

    Your schematic shows the TFP403, not the TFP401.

    Can you share waveforms of the DVI input? Also, can you share the datasheet for your display?

    Regards,

    I.K.

  • Hello I.K:

    I am sorry. it's my fault. I forgot to change the TFP401 in I/F ic form to 403.
    The schematic is correct, not TFP401. It is TFP403.
    Did I make some mistakes in the design of TFP403?

    Because our company does not allow me to provide the display module data sheet. Therefore, I cannot upload it, and I cannot ask you to help me solve some problems.

    Also, I don't have a high-speed oscilloscope or advanced protocol analysis equipment to measure fluctuations. You know that some companies always say that we have no budget.

    Regards,

    Simon



  • Hi Simon,

    The schematic looks okay for TFP403. You also want to make sure you have the control settings correct. 

    Is PIXS low for 1-pixel/clock?

    Is PD# high for normal operation?

    Does OCK_INV match your display panel settings?

    Also, now that you mention it, the oscilloscope you're using in the waveform picture your provided does not have enough bandwidth to correctly measure the DCLK signal, so that may be why it looks like that. You need a scope with a bandwidth of at least 500 MHz. 

    Regards,

    I.K. 

  • Hi I.K.

    First of all, much thanks for your kindly support.

    Yes, I found the waveform issue which cause my scope band width too small.
    The setting of the TFP403 list at below

    OCK_INV: High
    nSTAG: High
    PIXS: Low
    ST: High
    nPD: High

    My display module resolution is 1280x1024 @ 30 Hz and timing setting list at below

    HFP:48
    HSW: 112
    HBP: 248
    VFP: 1
    VSW: 3
    VBP: 38

    I'm not sure the TFP403 support this resolution or not.

    Now, I'm think the horizontal missing line was cause by timing setting.
    I will keep trying adjust the timing setting and updating here to share with you.

    Much thanks,

    Simon

  • Hello I.K.

    The timing capture list at below. I found the pclk a little strange. Would you please help to check?

    TFP403 Timing capture

  • Hi Simon,

    I agree that clock looks strange. The rest of the signals look okay though. I'm not sure what would cause that other than some issue with the DVI clock input.

    Regards,

    I.K. 

  • Hello I.K.

    Good day. I'm still try to find the issue of the pclk. I think this may the root cause issue of the horizontal missing.
    Do you know how TFP403 generates the PCLK signal?
    Because I didn’t find any relevant information on the datasheet.

    By the way, I connect the Pin1(DFO) to gnd. Will this have any different effects?

    Much thanks, 

    Simon

  • Hi Simon,

    The PCLK is generated from the input DVI clock. You can reference the "TFP403 clocking and data synchronization" section of the datasheet for more details. DFO held low is fine. PCLK will output continuously during both active and blanking regions, and that's how most applications will be configured.

    Regards,

    I.K. 

  • Hi I.K.

    Morning and evening.

    I found the PCLK's duty will reduce to 25%. But I really no idea what will cause this issue.

    Will it causing by impedance doesn't match?
    Is it possibly adjust it by outside circuit?

    Because I found the same setting with different frame rate the horizontal missing line will different.

    More effect with higher frame rate. (Reduce horizontal missing line)

    Hope you can give me some hint.

    The reduction of PCLK cycle is about 7us. But it does not happen at a fixed location. This is very strange.
    Have you ever this experience?

    Much thanks,

    https://drive.google.com/drive/folders/1Ttt3ZTxudA8oBjWAPk6Mp3Utg9x8dejr?usp=sharing

  • Hi Simon,

    Can you confirm that the input video stream does not contain any audio? Also, we really need to see the quality of the DVI CLK. If we cannot confirm that the DVI CLK input is fine, then everything else is just speculation.

    Regards,

    I.K. 

  • Hello I.K.

    First of all, thank you very much for your support.

    I finally found the root cause.

    OMG.. This is caused by crosstalk of the boost circuit noise through GND.
    Sorry for wasting your time.

    Finally, I can display the correct video through the external power supply, and the HDMI and video signals are also good.

    Thank you again for your patience and assistance

    Simon

  • Hi Simon,

    Great news- glad you found the root cause!

    Regards,

    I.K.