DS90UB954-Q1: 100M mipi CLK input from 953 but 200M mipi CLK output

Amelie Zheng

Part Number: DS90UB954-Q1

Hi Team,

My customer now use 2*953+1*954.

May I ask the calculation between mipi CLK output in 954 and mipi CLK input in 953?

Customer found that the input mipi CLK in 953 is 100MHz but the output mipi CLK in 954 is 200MHz. Why the mipi CLK change?

Does 954 only support 200/400/800/1600MHz CLK and the minimum is 200MHz?

over 4 years ago

0 Hamzeh Jaradat over 4 years ago

TI__Guru** 107380 points

Hello Amilie,

MIPI CLK on 953 and 954 are not dependent of each other. Each device runns at a different MIPI data rate/CLK.

953 has a min MIPI CLK = 40MHz, and max = 416MHz.
954 has a min MIPI CLK = 184MHz, and max = 832MHz.

0 Amelie Zheng over 4 years ago

TI__Genius 10865 points

Hi Hamzeh,

Does it mean the value of mipi CLK could be configured through register? But we can't find such a register in dartasheet.

0 Casey McCrea over 4 years ago in reply to Amelie Zheng

TI__Guru** 103215 points

Hello Amelie,

The MIPI clock on the input to 953 is not generated by 953, so not programming is needed based on the MIPI input rate to the 953. On the 954 side, the CSI-2 rate is configurable based on section 7.4.21 of the 954 datasheet.

Best Regards,

Casey

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DS90UB954-Q1: 100M mipi CLK input from 953 but 200M mipi CLK output