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DS90UB949-Q1: FPD3_LINK_RDY bit is randomly lost and the display flashes black momentarily

Adam Silva
Prodigy 105 points
Part Number: DS90UB949-Q1
Other Parts Discussed in Thread: DS90UB948-Q1

Hi,

I have a design using the DS90UB949-Q1 IC.  It is linked with a DS90UB948-Q1 within an LCD panel.  My display resolution is 1920x1200 @ 60Hz so I have an HDMI video input at 1920x1200 @ 60Hz and am utilizing the transmitter in dual-link mode.

I am occasionally seeing the LCD screen flash black momentarily and then returning to normal. The flash is only a fraction of a second. What I have found is that when this flash occurs the DUAL_STS register indicates that the FPD3_LINK_RDY bit has changed to 0 which would indicate that the FPD-Link III has lost detection of a valid downstream connection and/or momentarily lost determination of the capabilities for the downstream link. The remaining bits within the DUAL_STS register remain correct.  I am seeing the register temporarily change from 0xCD (the correct status) to 0x4D (the incorrect status).

What could be causing the valid downstream connection to momentarily go away and then recover on its own?  Is this an error occurring within the LCD panel design involving the DS90UB948-Q1 or can this be attributed to an error occurring with the DS90UB949-Q1?

Thanks,

Adam

  • 0
    TI__Guru** 103215 points

    Hello Adam,

    Can you please monitor the LOCK pin on the 948 to see if the link is losing LOCK when these flashes occur? 

    What kind of cable is used here between SER and DES?

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    Prodigy 105 points

    Hi Casey,

    I will begin monitoring that.

    We are using a custom cable design that utilizes Leoni Dacar 636-2 raw cable with HSD+2 connectors on each end.  It is 1 meter long.

    If we are losing the LOCK pin, what would that indicate is happening?

    Thanks,

    Adam 

  • 0 in reply to Adam Silva
    TI__Guru** 103215 points

    Hello Adam,

    If you are losing LOCK, it would indicate an issue with the link between SER/DES which could be linked to several different causes:

    - Issues in either the SER/DES HW design including power, MODE strapping, component selection for surrounding passives, etc. 

    - Issues in the 949 PCLK either being discontinuous, having high jitter, or being at an unsupported PCLK frequency

    - Issues with the high speed channel design (PCB/Connector/Cable) causing poor IL/RL performance in the high speed link  

    Best Regards,

    Casey