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TUSB4041I: Timing Requirements

FRANK1
Expert 8555 points
Part Number: TUSB4041I
Other Parts Discussed in Thread: TUSB8042A

Hi Team,

I have a query on the timing requirements for TUSB4041I and TUSB8042A.

The Power-Up　Timing　Requirements　is described below.

· TUSB4041I should start VDD33 before VDD
· TUSB8042A should start VDD before VDD33

This is really different between each other.
Is that right?

Or is it just a mistake?

  • +1
    TI__Guru 60870 points

    Hi Frank,

    There is no discrepancy, however the diagrams are different but explained in the notes.

    In summary:

    There is a requirement (note [1] ) in the datasheet specifying VDD33 to ramp after VDD11 if a passive reset circuit is used.  This requirement is meant to prevent the case where a customer ramps 3.3V before 1.1V and the internal pullup on GRSTz to 3.3V rises allowing the passive reset to complete before the 1.1V rail even powers on, leading to an invalid reset.  In practical application, most implementations have 3.3V and 1.1V ramp simultaneously (or within us) and include a large enough cap on the passive reset circuit pin to allow for reset to be held low for the required time after the power rails are stable. This is the case on the evaluation modules.   The capacitor on the GRSTz pin will vary depending on the ramp times in the platform.  1 uF is acceptable for many applications, 2.2 uF would give more margin if they have slower ramp times.

    If there is an active reset circuit in the design, which would not rely on the internal pullup resistor on GRSTz, then power rail sequencing does not matter.

    Regards,

    JMMN