SN65DSI86: Issues with some monitors

Arturo Esteban Vazquez Gutierrez

Part Number: SN65DSI86

Hello,

We have been working on a DisplayPort over USB-C design which uses the SN65DSI86 MIPI DSI to eDP bridge and an i.MX processor, originally, the IC REFCLK pin was tied to ground, for this case on the CPU side we received the monitors EDID and then we adjusted their pixel clock to the closest one that matches the equation shown below.

This make our board compatible with several monitors, but we noted that there was a group of devices that didn’t display image when performing this “downscale”.

Then, we decided to place a 27MHz oscillator on the REFCLK pin, as per our understanding this will remove our pixel clock limitations.

On our latest board revision which has the external oscillator, most of the monitors that didn’t work on the past now can display image correctly, but we have noted that some screens “blink” when sending image.

For example, originally, when connecting our board to a 2K display which requires a 241.5 MHz pixel clock, our CPU provided a downscaled 162 MHz clock and the screen worked with no problem.

Now with the external oscillator the same monitor is working with the 241.5 MHz pixel clock with no need of downscaling, but it blinks as shown on the attached video.

Is this a known issue?

Is there anything that we could do to fix this?

Any guidance would be appreciated,

Best regards,

Esteban V.

over 4 years ago

0 David (ASIC) Liu over 4 years ago

TI__Guru**** 176811 points

Esteban V.

Can you dump out the DSI86 status registers 0xF0 to 0xF8 and see if there are any errors, particularly on the DSI side, being reported?

With the clock frequency changes from 162MHz to 214.5MHz, have you also checked the setup and hold timing on the DSI side and make sure the timing is still met?

Thanks

David

0 Arturo Esteban Vazquez Gutierrez over 4 years ago in reply to David (ASIC) Liu

Prodigy 200 points

Hello David,

Thank you for the quick response, please look to the i2c status registers of our board testing both pixel clocks for the 2K resolution, there can be seen some DSI errors when using the 214.5 MHz clock.

214.5 MHz pixel clock status registers.

[0xf0] = 0x00000003
[0xf1] = 0x00000023
[0xf2] = 0x00000000
[0xf3] = 0x00000000
[0xf4] = 0x00000001
[0xf5] = 0x00000000
[0xf6] = 0x00000042
[0xf7] = 0x00000000
[0xf8] = 0x00000001

162 MHz pixel clock status registers.

[0xf0] = 0x00000000
[0xf1] = 0x00000000
[0xf2] = 0x00000000
[0xf3] = 0x00000000
[0xf4] = 0x00000001
[0xf5] = 0x00000000
[0xf6] = 0x00000000
[0xf7] = 0x00000000
[0xf8] = 0x00000001

It seems that this issue is directly related to our CPU instead of the SN65DSI86, right?

Is there anything that can be done on the DSI side of the bridge to handle this?

Looking forward to your comments,

Best regards,

Esteban V.

+1 David (ASIC) Liu over 4 years ago in reply to Arturo Esteban Vazquez Gutierrez

TI__Guru**** 176811 points

Esteban V

You can try the adjustment of the RX EQ located at register offset 0x11 and see if it helps.

With a faster clock frequency, your have less setup and hold up timing margin. I would check and see if the setup and hold timing is still meeting the DSI86 requirement.

Thanks

David

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SN65DSI86: Issues with some monitors