Other Parts Discussed in Thread: DP83640, DP83825
I am designing a new Sitara board based on AM4372BZDNA80 processor with two RMII Ethernet ports.
I am considering using two DP83825I devices for PHYs, and trying to determine the best REFCLK architecture.
1. One PHY in master mode w/ a 25MHz xtal, & use 50MHz output to drive other PHY in slave mode and also drive both REFCLK inputs to AM437x. Is there sufficient clock drive strength for this?
2. Each PHY is in master mode w/ its own xtal and its own 50MHz output to respective uP REFCLK input
3. Use external 50MHz clock osc chip which drives both slave PHY's and also uP REFCLK inputs. (or could use 25MHz osc to both PHYs in master mode and use respective 50MHz outputs to uP).
#1 would be our preferred solution due to cost. Is this workable?