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DP83867IS: Clock Input Timing in Two-Supply Mode

Darren (FAE)
Expert 5483 points
Part Number: DP83867IS

The DS specifies there are no power sequence timing requirements when in Two-Supply Mode. 

Q1: Should device be held in reset until both power rails come up?

Q2: in Two-Supply mode (2.5V and 1.1V) the CLK still needs to be a 1.8V signal, yes?

Q3: Is there a timing requirement for CLK? Can 1.8V CLK be applied before 2.5V, etc...

Q4: Should device be held in reset until both power rails, and CLK are all up?

EDIT: For Q3/Q4 above, if device needs to be held in reset until supply rails and CLK are up, how long after CLK is supplied before device can safely be released from reset? What if device reset is released on a CLK edge, etc?

  • 0
    TI__Genius 16030 points

    Hello,

    Answers in order of the questions :

    A1 : Not required. But toggling resetn low for >5us after all supplies and oscillator is stable takes care of any issue with clock start up.

    A2 : Yes it should be 1.8V or you may use specified cap dividers to make it 1.8V if oscillator is on higher voltage.

    A3 : Clock should be stable before supplies are ramped up. If this is not possible then make resetn pin low for > 5us after the oscillator is stable.

    A4 : Answer in A1.

    --

    Regards,

    Vikram