• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 604 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DP83TG720S-Q1: Whether we have 1000M with 1588v2?

DP83TG720S-Q1: DP83TG720S-Q1

Didier BASSET
Prodigy 10 points
Part Number: DP83TG720S-Q1

Hi team,

I don't see in the latest data sheet of the PHY DP83TG720S-Q1 anything about the SFD 1588 compliance .  How can we use it ?

  • 0
    TI__Genius 16030 points

    Hello Mr Basset,

    720S does not support start of frame detect. Though latency numbers are low (as described in datasheet) and that can enable 1588 time stamping in the processors/MAC.

    --

    Regards,

    Vikram

  • 0 in reply to Vikram Sharma
    Prodigy 10 points

    Hello Vikram,

    So the anwer of Justin Lazaruc in an other topic of the forum about IEEE 1588 compliance "The DP83TG720 supports the 1588 SFD pulses but not the entire standard" means in fact that low latency of the PHY helps to have an accurate time stamping even if it's done at the MAC level ?

    May be I have missed something in the data sheet, but there is only the maximum values for the latency time, what is the min value or the accuraty of this latency ?

    One other question, do we have to be in "RS-FEC bypas mode" to optimize the latency jitter ?

     Regards,

    Didier.

  • 0 in reply to Didier BASSET
    TI__Genius 16030 points

    Hell Didler,

    Team is looking at the data to share the latency variation with you. And yes we have RS-FEC bypass mode as mentioned in the latency section in the datasheet on ti.com

    --

    Regards,

    Vikram

  • 0 in reply to Vikram Sharma
    TI__Genius 16030 points

    Hello Didler,

    It took a while to work with team to find the required latency variation you were looking for. In the current datasheet, we have put the worst case number + extra margin. But we understand that you and some other customers are also looking at variation of latency and not just the worst case number. So to highlight the variation in the latency, following are the numbers with extra guard band removed from max and min numbers added to the table :

    Receive latency   min typ max Units typ
    rgmii default 6.308 6.324 6.34 us 6.324
    rgmii with FEC bypass 298 314 330 ns 314
    sgmii default 6.354 6.37 6.386 us 6.37
    sgmii with FEC bypass 343.5 359.5 375.5 ns 359.5
    Transmit latency            
    rgmii default 0.561 0.577 0.593 us 0.577
    rgmii with FEC bypass 561 577 593 ns 577
    sgmii default 0.618 0.634 0.65 us 0.634
    sgmii with FEC bypass 625 641 657 ns

    641

    We are doing some extra silicon characterization and will update the datasheet.

    --

    Regards,

    Vikram