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DP83849I: Sampling Timing of Strap Option Pin

user5286503
Prodigy 210 points
Part Number: DP83849I

During the RESET_N pin is LOW (Reset Enable), can we set voltage of Strap option pins to Hi-Z 

(It could be the middle between HIGH level and LOW level)?  

*Then we set voltage of Strap option pins to HIGH or LOW before de-asserting the RESET_N pin.

We connect the DP83849I's strap option pin (Internal weak pulldown) to FPGA's I/O pin which

is weak pulluped during FPGA configuration.  So after power up and during RESET_N is LOW,

the strap option pin's voltage would be the middle between HIGH level and LOW level. 

We would like to check if this behavior is not an issue.

*The RESET_N pin is de-asserted after completion of the FPGA configuration.

According to the Figure 4-1. Power Up Timing in the DP83849I Datasheet, Strap option pins

are sampled after de-asserting the RESET_N pin.  So we believe that the above behavior

is not an issue.

Thank you.

  • 0
    TI__Genius 16030 points

    Yes strap options pin can be high-z when resetn pin is low. If the strap voltages is being set to the required value before reset is released, then strap will get latched to correct value.

    --

    Regards,

    Vikram

  • +1 in reply to Vikram Sharma
    Prodigy 210 points

    Dear Vikram-san,

    Thank you for your quick response.

    Just making sure, could you check the following?

    Regarding the AN_EN, AN[1:0]_[A:B] pin, the following comment is shown on the 3.2.7 Strap Options in the DP83849I Datasheet.

    "The float/pulldown status of these pins are latched into the Basic Mode Control
    Register and the Auto_Negotiation Advertisement Register during Hardware-Reset."

    What does [during Hardware-Reset] mean?

    It means the RESET_N pin is LOW level? or just after de-assertion of the RESET_N pin?

    If former is correct, will the above option pins be sampled during the RESET_N pin is LOW level?

    Thank you.

    Best regards,

    Takashi

  • 0 in reply to user5286503
    TI__Genius 16030 points

    Hello Takashi-san,

    Straps are latched just after releasing of resetn pin from the low state. Toggling of resetn pin is the hardware reset.

    --

    Regards,

    Vikram