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SN65DSI86-Q1: SN65DSI86-Q1 Unlock PLL issue

TT_Chin
Expert 2025 points
Part Number: SN65DSI86-Q1
Other Parts Discussed in Thread: SN65DSI86

Hi Sir,

I design SN65DSI86 to do the function of MIPI-DSI to eDP.

But it occur PLL unlock issue after setting the DP_PLL enable in the register.

It seems like the below issue before.

https://e2e.ti.com/support/interface/f/interface-forum/846730/sn65dsi86-questions-for-sn65dsi86-pll-unlock-issue?tisearch=e2e-sitesearch&keymatch=sn65dsi86%2520PLL#

Could you help me check the issue ?

Thank for your help!

Sincerely,

Shichin

  • 0
    TI__Guru**** 176261 points

    Shichin

    Are you using REFCLK or DSI clock as your clock source? Can you measure the clock using a scope?

    If using the DSI clock as the clock source, any one of the following DSI A clock frequencies can be used: 384MHz, 416MHz, 460.8MHz, 468MHz, or 486MHz.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Expert 2025 points

    Hi David,

    I use REFCLK (27MHz) as our clock source and I have measured 27MHz clock into  SN65DSI86.(see the picture below)

    By the way, if any possible that I can get free EVM module from website for the test ?

    Thanks!

    Sincerely,

    Shichin

  • 0 in reply to TT_Chin
    TI__Guru**** 176261 points

    Shichin

    1. Are you setting GPIO[3:1] to 3’b011 for the 27MHz crystal clock frequency?

    2. Can you double check the power up sequence and make sure the 27MHz clock is stable when the DSI86 came out of the reset?

    Please check with TI local FAE on obtaining the free DSI86 EVM.

    Thanks

    David