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TUSB8042: TUSB8042 - unused pin / features

Part Number: TUSB8042

Hello Team,

we are planning to use the TUSB8042 on a board but some pins will not be used.

Can you confirm the understanding below?

unused USB_SS_TX output pins can be left floating.

The datasheet says:

    When the upstream port is connected to an electrical environment that only supports

   full-speed/low-speed connections, SusperSpeed USB and high-speed connectivity

   are disabled on the downstream ports.

So, I am guessing that the unused USB_SS_RX inputs pins can also be left floating.

Is this correct?

While we don’t need power from upstream, I suppose we will still connect

the voltage divider to USB_VBUS monitor input.

Special requirements for the voltage power sequencing?

Thanks,

SunSet

  • Hi SunSet,

    Yes, unused SS pins should be left unconnected.  USB_VBUS is a detection input and should be high whenever an active host is connected.

    There is a requirement in the datasheet specifying VDD33 to ramp after VDD11 if a passive reset circuit is used.  This requirement is meant to prevent the case where a customer ramps 3.3V before 1.1V and the internal pullup on GRSTz to 3.3V rises allowing the passive reset to complete before the 1.1V rail even powers on, leading to an invalid reset.  In practical application, most implementations have 3.3V and 1.1V ramp simultaneously (or within us) and include a large enough cap on the passive reset circuit pin to allow for reset to be held low for the required time after the power rails are stable. This is the case on the evaluation modules.   The capacitor on the GRSTz pin will vary depending on the ramp times in the platform.  1 uF is acceptable for many applications, 2.2 uF would give more margin if they have slower ramp times.

     

    If there is an active reset circuit in the design, which would not rely on the internal pullup resistor on GRSTz, then power rail sequencing does not matter.

    Regards,

    JMMN

  • Thanks,

    SunSet