DS90UB934-Q1: YUV422 pass through

Hello Yuta,

did you make sure your configuration is similar for both SER and DES? i.e. using the same MODE?

Question: How did you split the signal at the SER output to fed both, the DES and the SoC?

Hello Hamzeh,

Thanks for your answer.

Customer set the 934 as RAW10 mode by MODE pin resistor.

But they are not sure what the mode of 933. Can you let me know how to set the mode of 933?

The SoC is connected with D[0:9], HSYNC, VSYNC, PCLK line.

Thanks,

Yuta Kurimoto

Hello Hamzeh,

The Table 7-2 shows the setting either "PCLK from imager" or "External Oscillator". Customer will use PCLK mode.

The Table 7-3 shows the setting of forward channel frequency. But customer use PCLK so this table 7-3 doesn't relate.

Can you let me know how to set RAW10 mode for 933?

Thanks,

Yuta Kurimoto

Hello Yuta,

If you chose the correct clocking mode, your SER will be configured autimatecaly by the DES via back channel. To make sure your SER is in the right Mode, you can read back register 0x05.

Hello Hamzeh,

Thanks for your clarification.

Customer confirmed that the both 933 and 934 are set RAW10 mode. So these are same mode.

Is there any other thing which they need to check?

Thanks,

Yuta Kurimoto

Question,

How is the parallel LVCMOS Signals are divided between SoC and DES? May be this is the reason for quality digradation of the signal!

Hello Hamzeh,

I will send you the circuit diagram by email directly.