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DP83867E: RX_CTRL output is abnormal

Part Number: DP83867E


Dear Team,

We use the DP83867E as an RGMII PHY, and connect to our MAC Controller, but we observed an anomaly in the RX_CTRL output through the oscilloscope. Detail configuration is as follows:

1. Enable the LOOPBACK Bit of Basic Mode Control Register

2. Config the DUPLEX MODE of Basic Mode Control Register to "Full Duplex operation" 

3. Config the TX FIFO Depth and RX FIFO Depth of PHY Control Register

4. Config the RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY of RGMII Control Register to "RGMII transmit/receive clock is shifted relative to transmit/receive data"

5. Config the RGMII_TX_DELAY_CTRL and RGMII_RX_DELAY_CTRL of RGMII Delay Control Register to 4.00 nS

The Figures as follows are captured by the Logic Analysis. As you can see from the Figure_1, the TX_CTRL from MAC Controller is always output High Level, But the RX_CTRL from DP83867E will generate a Low Level pulses periodically. Cycle time is about 321uS and Low Level duration is 80nS. And the Data is 0x9, 0x9. More detail info please see the Figure 2 and 3

Figure_1Figure 2Figure 3

The output of RX_CTRL is not what we expected, and it caused the MAC Controller receive the wrong data (or means lost some valid data)

Please explain this phenomenon and provide a solution. Thanks !

  • Hi Ezio,

    To better troubleshoot your issue, can you upload your exact script?

    I would also like you to provide a register dump of all registers 0x00 to 0x001F, 0x0032, 86, 6E, 6F.

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “AS IS” and “with all faults”, and it is subject to TI’s Important Notice (www.ti.com/.../important-notice.shtml).

  • Hi Joe,

    Sorry we can't disclose our source code, but we can provide results for reading PHY registers. Screenshot as follows:

    Register 1Register 2

  • Hi Ezio,

    When you configure the PHY for analog and digital loopback do you experience the same issue?

    Try forcing 100mbps and enabling digital loopback

    0x0000 = 0x0100 // force 100mbps

    0x0016 = 0x0004 // enable digital loopback

    Then try forcing 100mbps and enabling analog loopback.

    0x0000 = 0x0100 // force 100mbps

    0x0016 = 0x0008 // enable analog loopback

    Please let me know if you experience the same results.

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

  • Hi Joe,

    The result of the Digital Loop is still Fail, but the captured waveform is not completely consistent with that of the MII Loop. The screenshot is as follows:


    In addition, there are abnormalities in the configuration of Analog Loop. It can be seen from the captured waveform that RX_CTRL has not been output, and from the Register read, the Link Status has not been set.The screenshot is as follows:

  • Hi Ezio,

    Are you able to provide your schematic so that I can better troubleshoot your issue?

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

  • Hi Joe,

    If a MII Loop or Digital Loop is selected, does the PHY check the correctness of the data?
    We are quite puzzled that we have configured the TX CLOCK DELAY of PHY, but if it is Timing Violation, RX_CTRL should not be periodically invalid. And the skew of the data and clock should be less than 4nS according to the picture captured by the oscilscope (see the figure below).


    We can't provide a complete Schematic, but the Schematic for DP83867E is as follows:

  • Hi Ezio,

    We should mention that when using analog loopback, a 100 ohm differential termination is required on the MDI. 

    In digital loopback, the data passes through the PCS block of the PHY as noted by Figure 19 in the datasheet. If the data cannot be decoded, it will generate RX errors and the error counter in register 0x15 will increment. 

    Currently are there any errors in communication? Is communication still clean despite this RX_CTRL behavior, or is data transfer impacted?

    Thank you,

    Nikhil

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

  • Hi Joe,

    We have found the Root Cause, which is caused by abnormal reference clock frequency of MAC Controller. The TX_CLK frequency output by MAC is not the standard 25MHz, which causes the PHY to parse the data wrong.
    Thank you for your support, I will close this issue!