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DP83822IF: SD line logic level for LVDS compatibility

Expert 6760 points

Part Number: DP83822IF

Hi,

The TD_P, TD_M, RD_P, RD_M are specified as PMD outputs and are in line with most LVDS manufacturers.

What about the SD Line (Pin_24/LED_1_GPIO_1)? They can be sepcified as LVDS but also as LVPECL. 

Does this have to come in / be set as LVPECL in order to work?

Regards

Andreas

  • Hi Andreas,

    I have acknowledged your post and I will reach out to the team for an answer to your question. I hope to get back to you by Wednesday (4/28).

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

  • Hi Andreas,

    The DP83822IF SD Line has cmos i/o and is not differential.

    As long as you comply with vih, vil, voh, vol requirements for LVDS/LVPECL, your application should work.

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

  • One can find tables in the internet that specify LVPECL with VoH 2.4V and VoL with 1.6V whereas LVDS is specified with VOH1.475V and VoL 0.925V. So they have different thresholds..

    Now there are also optical fibre parts where Rd+/- TD+/-lines are directly specified with LVPECL. But this doesn`t fit with the PMD specification of DP83822IF. Any thoughts? would that require a different PHY?

  • Hi Andreas,

    I apologize for not being specific in my first response. I recommend you take a look at table 7.5 Electrical Characteristics in the datasheet.

    The SD output just needs to comply with the vih, voh, vil, ad vol requirements for the 822 in your respective Vddio section in this table.

    Please let me know if you need further clarification.

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

  • Hi Andreas,

    I haven't heard from you for some time. I will now close this thread and if you have any further questions please respond to this thread.

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

  • Hi Joe,

    this topic came up again resp. I am looking for some verification of the following:

    Is it correct that last line of table 7.5 specifies the swing of differential pairs? And for 100Base-FX that is allowed to be between 300 and 900mV? That way it would be compatible with LVDS (+/-350) as well as LVPECL(+/-800)? And Vcm resp. the nominal voltage would not be relevant? Only the swing?

    And the SD line must be in line with 3V3 VDDIO acording to datasheet which would be LVTTL or LVPECL. LVDS would be too low voltage wise?

    TODX2701AF says  LVPECL compatible in the datsheet, no more details, no swing. Can one assume that if above is followed that should work?

    Thank you & regards

    Andreas

  • Hi Andreas,

    Sorry for the delayed response. I hope to get back to you with answers to your questions by the end of Friday 5/21.

    Thank you for your patience.

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

  • Hi Andreas,

    You are correct. After configuring 0x0403 Line Driver Control Register (LDCTRL), you should be able to comply with those differential standards. 

    From EC table I see the SD pin requires a minimum swing of 2.0V with 3.3V Vddio. It is either active high or low just needs to meet the Vih and Vil requirements for an IO pin.

    As for the other part, if your 822IF Vod levels comply with LVPECL, the PHY should work with LVPECL devices. Generally, we cannot speak for a non-TI product.

    I would urge you to verify that the fiber transceiver swing is within 822IF specs of Jitter, transceiver timing requirements, and voltage levels. You may need to use pull-ups on the transceiver lines to adjust voltage levels. I have attached an image of the termination used when complying with LVPECL from the DP83TC822 EVM User's guide: https://www.ti.com/lit/pdf/snlu179 

    Please let me know if you need any additional information.

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)

  • Hi Andreas,

    I haven't heard from you for some time. I will now close this thread and if you have any further questions please respond to this thread.

    Kind Regards,

    Joe

    All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml)