HD3SS3220: TX2P/N has no signal out

is EN_MUX and EN_CC pin low? Can you take waveform on CC pin?

is this DRP? does it work when it connect to DFP?

It also missing a VBUS switch for DFP

EN_MUX and EN_CC pin is pull down.

This is DFP mode.

VBUS ：The 5V voltage is normal.

for DFP, you need VBus switch which is normally controlled by ID pin. Vbus will be turned on after an UFP is connected.

Hi Brian Zhou

What situation will happen if we provide 5V on VBUS before connecting to an UFP?

Thanks.

CC1/CC2 has changed, but DIR is always High

What situation will happen if we provide 5V on VBUS before connecting to an UFP?

ID pin will not go low and will be waiting for Vbus at 0v

Brian, thanks for your prompt reply.

Please also help to ask my colleague, Jun's, question.

What factor would cause DIR not changed to low even after CC2 has been changed its level to low?

DIR may wait for ID pin goes low as well

I assume you were mentioning this paragraph below and it is a piece of key information.

Are we able to make ID pin go low by controlling ENn_CC signal with the diagram below if we remain the structure of providing 5V directly without switching on by a switch when powering on?

We kind of fixed the issue yesterday and it is almost exactly like what you shared with us.

In our circuit design, we connect ID pin to our CPU and use another I/O pin to control a 5V power switch rather than connecting ID pin to the power switch directly and then modify our firmware to accomplish this behavior.

Now, we can see waveforms from channel 2 for reversible plugging.

Anyway, many thanks for your support.