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DS90UB941AS-Q1: 941 DOUT‘s Vod amplitude test

Sherry Liang
Genius 10255 points
Part Number: DS90UB941AS-Q1

Dear team,

Currently my customer test below parameter, but the test result is only around 650mV which is smaller 900mV. Is there any special requirements for below spec? The BW of the oscilloscope is 13GHz, sample rate is 40GSa/s, and the differential probe is 12GHz. We add the 100ohm, and we still connect to the display when testing. Once disconnect the display, there is no output on DOUT pin.

Thanks & Best Regards,

Sherry

  • 0
    TI__Guru** 103215 points

    Hello Sherry,

    The way that this parameter is tested doesn't match how a customer would really characterize the device so there is no need to measure this parameter in the system. The way this is tested is by sending a static high/low from the FPD driver and measuring the VOD. It is not the same thing as eye height which is probably what is being measured by the customer since by default the FPD driver will not be static 1/0. It will be toggling

    Best Regards,

    Casey 

  • 0 in reply to Casey McCrea
    TI__Genius 10255 points

    Hi Casey,

    Thanks for your reply!

    If my customer wants to make some test to prove their design is ok, do we have some recommended test items?

    In addition, we try to test the eye diagram, but the eye height is also lower than below specs. Below test result also have special test pattern, right?

    Thanks & Best Regards,

    Sherry

  • 0 in reply to Sherry Liang
    TI__Guru** 103215 points

    Hello Sherry,

    I presume that the customer is measuring this eye diagram at the output of the connector on the PCB? This eye height is referring to the launch amplitude of the signal from the output of the 941AS pins directly. If the measurement is done after the PCB/passives on the board, then you will see a reduced amplitude due to attenuation which is normal. Typically we do not recommend any need to verify the eye height for 941AS. The main characterization points to focus on for the 941AS device design would be:

    - Power supply levels, noise, and power sequence 

    - MODE pin strap levels 

    - DSI input characteristics including CLK jitter if using PCLK from DSI clock mode 

    - FPD-Link channel s-parameters including insertion loss, return loss, and impedance continuity between SER and DES 

    Best Regards,

    Casey