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TCA9800: SCL clock frequency check

Part Number: TCA9800

Hi Team,

Greeting! Customer wants to check with us whether below usage is acceptable or not?

Actual usage: 

I2C SCL clock frequency is 30kHz, VCCB is 3.3V. In this condition, what the max rise time for VCCB?

Below is datasheet screenshot about above part, just for your easy checking.

Waiting for your response.

B&R

Stanley

  • All values except fSCL(MAX) belong in the switching characteristics table. (For a requirement, a typical value would not make sense.)

    30 kHz is allowed. There is no requirement for the input rise time.

  • Thanks for your reply. I want to correct my above question. Since 30 kHz is allowed, does this clock still needs to meet tr(rise time) requirements when VCBB is 3.3V, below 270ns?

  • There is no tr requirement; tr describes the output signal. Any 30 kHz signal is allowed.

  • Thanks for the help Clemens!

    Stanley,

    Along with Clemens help, I've also notified a TI engineer to look at this thread.

    Regards,

    Eric Hackett 

  • Hi Stanley,

    The datasheet language is a little confusing when it says the minimum maximum frequency this device supports is 100 kHz. Essentially what this means is that this device can support the maximum capacitive load (400 pF) at 100 kHz. However this device can only support ~90 pF at 400 kHz.

    For Fast mode (400 kHz) the maximum rise time is 300ns and as you can see above the maximum load at 300ns for the TCA9800 is around 90 pF.

    As Clemens said you are allowed to run this device below 100 kHz, what will change is the maximum load allowed on the bus and technically the maximum rise times. What you are looking at in the datasheet is not a requirement of the device but how the device preforms at the specific load conditions and voltages.

    For 100 kHz the maximum rise time is 1000 ns. For 30 kHz you will have a little more wiggle room but as long as you stay under 1000ns and 400 pF you will be absolutely safe to run at 30 kHz.

    Best,

    Chris