TUSB7320: Noise occurs in the power supply

Do you have decoupling cap on power supply?

Yes. Decoupling capacitors are mounted.

Below is an excerpt of the schematic and layout.
Please let me know if you have any concerns.

Additional information.
The peripheral circuit diagram of TUSB7320 is shown below.

those small value caps (0.1uf 0,01uf) should be placed close to each power supply. Also check if ground pad is soldering properly.

I will answer about the confirmation result.

・Capacitor parts are wired within 5 mm of the power supply pattern.
・ Soldering was confirmed by X-ray analysis.

By the way, isn't it possible to wrap around from the XI terminal inside the TUSB7320?
Can you give me a document showing the wiring structure inside the TUSB7320?

don't think it's XI related, can you remove TUSB7320 and do the same test again?

Another way is to adding Ferrit Bead to filter noise

It says "remove TUSB7320", does this mean that TUSB7320 is not implemented? 

I mean just test power supply without TUSB7320 to see if device related

Hello Brian,

Thank you for your support comments.

When I checked the power supply, I found that noise did not occur when I changed rise time of VDD11. 

Specifically, the soft start constant of the VDD11 power device was changed to shorten rise time.

The waveforms before and after the change are shown below.

Is there a limit to the power startup time?
Do the three types of power supplies need to have the same slope for power rise?

Power rise waveform before change.

Power rise waveform after change.

so the 2nd waveform fixed the issue? We don't have ramp time spec yet.

Can you just change delay between VDD11 and 3.3V and see any impact?

Hi Brian,

Yes. The problem was fixed in the second waveform.

>Can you just change delay between VDD11 and 3.3V and see any impact?

=> I changed the slope of the power rise of VDD11. The result is a problem when the ramp time of VDD11 is long.

Do you know anything from this result?

The waveforms under normal conditions and the waveforms when problems occur are shown below.

The cursor in the waveform is set to the minimum operating voltage.

①Normal condition (When no problem occurs)

②Waveform when a problem occurs Part 1

③Waveform when a problem occurs Part 2

Regards, 

Masahito

can you  just start VDD11 earlier but keep same ramp rate with your design?

In our design, VDD11 cannot start earlier.

This issue seems to be caused by the difference in the timing of reaching the operating voltage.

Our design uses the same LDO(TPS74401) as the reference design (Figure 13. Reference Design 4).

The reference design does not implement a soft start capacitor, but we do implement a soft-start capacitor (0.001uF).

The soft-start capacitor is mounted in consideration of the inrush current.

Please tell me if there is a reason why the reference design does not have a soft-start capacitor.

The circuit diagram of TPS74401 is shown below.

1. Our design

2. Reference design

100us ramp time should be good enough for TUSB7320, that's why it's floating

Thank you for your answer.

I have 3 questions.

1. 　"100us ramp time should be good enough for TUSB7320",　Is there a provision to lamp up within 100us for the answer?

2. 　What is the 100us lamp time rule for which power supply (VDD11 or VDD33)?

3. 　If there is a regulation, which document has it?

sorry, we didn't see this issue before and don't have regulation between VDD11 and VDD33. We only have timing regulaton between power supply and clock signal and reset

Let me check Power-Up and Power-Down Sequencing.

Our system is monitored by Watchdog timer. At that time, the power supply (1.1V, 3.3V) and RCIE_REFCLK are not cut off.
Is it necessary to temporarily stop the TUSB7320 power supply (1.1V, 3.3V) and PCIE_REFCLK based on the 9.1.1 Power-Up Sequence in the data sheet when resetting the system?

from power sequence, power supply and 48Mhz clock should be ready before GRST reset, PCIE_REFCLK should be ready before PERST.

but you don't need to stop them as long as you meet above requqirement

Thank you for your answer.

Let me ask you two questions.

1)
Which reset (GRST or PERST) must be asserted when resetting the TUSB7320 without shutting down the power supply?

2)
Are there any restrictions on the boot order for GRST and PCIE_REFCLK?

GRST is for TUSB7320 reset,

there is no boot order between GRST and PCIE_REFCLK

Could you please give me a block diagram inside the parts of TUSB7320?

Since the operation status differs depending on the power-on order, I would like to check which function inside the component operates when each power supply (VDD11, VDD33) is turned on.

let me check if can send block diagram to customer.

Thank you for your support.

Please confirm the provision of the block diagram.

Could you please provide the response deadline on 6/7 (Mon)?

Hi Hisashi:

    Pls. accept my friendship request  and I can send block diagram to you.

Regards,

Brian

Thank you for providing the block diagram.

However, I cannot receive the block diagram.

Could you tell me how to receive it?

you can either send your email address here, or accept my friendship request.

Regards,

brian

Thank you for your answer.

I don't know how to receive a friendship request.

I received a friendship request email.

I clicked Accept, but the block diagram is not attached.

Please tell me how to receive it.

you will receive email like this and click accept 

Thank you for your answer.

When I clicked as instructed, the screen below appears and I don't know how to proceed.

Please tell me about the power supply (VDD11 / VDD33) of TUSB7320 and the boot order of 48MHz.

48MHz uses a crystal oscillator from the outside.

Hi Hisashi:

     Block diagram was sent to Satoshi.

    For 48Mhz crystal, which will be turned on by VDD33. Keep GRST# low, until 48Mhz clock is stable.

Regards,

Brian

thank you for your answer.

I will receive the block diagram from Mr. Yoshida.

It wasn't the answer I expected, so let me ask you again.

Is there a rule as to which of the 48MHz crystal and the power supply (VDD11 / VDD33) starts first?

I saw the block diagram.

It wasn't the block diagram I expected.

What you want to know is a block diagram that allows you to see which functions inside the component operate when each power supply (VDD11 / VDD33) is input to the TUSB7320.

The block diagram I received did not show the elements of the power supply.

Hi Hisashi:

    We don't have the detailed block diagram for each function with power supply.

    But VDDA33 is for USBPHY and PICe PHY, VDD11 is for digital core and VDD33 is for IO.

    There is no rule for 48Mhz crystal and VDD11/VDD33, since Crystal will not start until VDD33 is meet min valid value.

   But GRST should be low until VDD11/VDD33/VDDA33 is on and 48Mhz clock is ready.

Regards,

Brian

Thank you for your answer.

In the answer It says "There is no rule for 48Mhz crystal and VDD11 / VDD33".

On the other hand, isn't the description "until VDD11 / VDD33 / VDDA33 is on and 48Mhz clock" intended in the order of VDD11 / VDD33 / VDDA33⇒48MHz clock?

if you supply external 48Mhz clock, it can be start early than power supply. But Crystal is powered by power supply.

thank you for your answer.

From the answer, the external 48MHz clock supply can be started faster than the power supply (VDD11 / VDD33).

In that case, is there any problem with latch-up by inputting a 48MHz clock from the outside before supplying power?

Hi Hisashi::

     latch up is triggered by over voltage or current injection. if clock signal is within IO spec. It will not cause latchup. But still suggest to start clock after power up during application.

regards,

brian

Let me check the power supply and clock-on sequence again.

1)
In 9.1.1 Power-Up Sequence of the data sheet

2. describes power-on, and 3. describes clock-on.
Then, since there is a description of 2. 3., I think that it shows the order, but how about it?

2)
If there is no boot order of VDD11, VDD33, 48MHz in the answers so far, how is it guaranteed as the internal specification of the device?
For example, if there is no boot order, will there be no current leakage at the other power terminal when one power is turned on?

In addition, 48MHz uses a clock oscillator.
I think that your evaluation board etc. uses a crystal units.

Hi Hisashi::

     Most important two items here:

1: VDD11 must be early than VDD33.

2:  GRST keeps low until power supply and clock oscillator or crystal stable.

    when clock is up a little early than power supply, leakage will be short and will not hurt device. What we need to avoid is clock is always on when power supply is off, which will hurt device.

Regards,

brian

Hi Brian：

Thank you for the important information.

Let me ask you an additional question.

a)

Our power-on waveform is attached.

Please comment on the startup procedure and power-on timing regarding the relationship between VDD11, VDD33, and 48MHz.

Could you please show me the recommended timing for turning on the 48MHz clock?

Green ・ ・ ・ VDD33

Yellow ・ ・ ・ VDD11

Red ・ ・ ・ 48MHz OSC

b)

Please tell me the answer of "VDD11 must be early than VDD33."

The specifications of VDD11 and VDD33 are described in the data sheet

As shown in the above waveform, is it okay if VDD11 starts up later than VDD33 starts up (rises from 0 [V])?

Or does VDD33 need to start booting (rising from 0 [V]) after VDD11 has finished booting (0.99V or higher)?

By the way, the circuit diagram of your evaluation board seems to be a circuit configuration in which the power supply supplied to VDD33 has a faster start-up start (rise from 0 [V]) than VDD11.  

c)

About the comment "when clock is up a little early than power supply, leakage will be short and will not hurt device. What we need to avoid is clock is always on when power supply is off, which will hurt device."

・Which does the power supply indicate VDD11 or VDD33?

・Also, please tell me how long "a little early" is.

・Are you saying that 48MHz will be turned on after the power supply (VDD11 → VDD33) is started up?

d)

By the way, where can I find information on the power-on order in the data sheet?

Regards,

Yoda

a: what is blue signal XHCI_CLKIN_OE? can you capture GRST# in the same picture

b: sorry, I'm confused with TUSB1310. For TUSB7340, VDD11 can be start late than VDD33. Pls. check  TUSB7340 EVM design.

c: power supply is VDD11/VDD33. a little early means within 100us.

d; you can find power on sequence on datasheet page 104

Hi Brian：

Thank you for your answer.

We will answer the questions you have received.

a) Blue is not XHCI_CLKIN_OE. Blue was remeasured as GRST #.

Green・・・VDD33

Yellow・・・VDD11

Red・・・GRST

Blue・・・48MHz OSC

Let me ask you again.

e) Let me check the clock input timing.

Is it necessary to input 48MHz after VDD11 and VDD33 are started as shown in the waveform below?

See attached file（See white arrow）

f)If there is no boot order of VDD11, VDD33 in the answers so far, how is it guaranteed as the internal specification of the device?

For example, if there is no boot order, will there be no current leakage at the other power terminal when one power is turned on?

Regards,

Yoda

Hi Brian：

When will you get the answer?

This is in a hurry.

If you cannot answer, please tell me the deadline.

Regards,

Yoda

a: waveform for a is good power on sequence.

e: It's not necessary to move 48Mhz clock . If BLUE is GRST#, it should be low until CLK/power is stable.

f: there should be protection diode inside between 1.1v and 3.3v to avoid leakage when one pwoer supply is on and the other is off.

Hi Brian：

Thank you for your prompt reply.

In the waveform of e), blue is not GRST #.

About " It's not necessary to move 48Mhz clock."

Is it possible for the TUSB7320 to be damaged or malfunction if 48MHz is repeatedly applied before VDD11 and VDD33?

The intention of the confirmation is to confirm whether the 48MHz input timing must be after VDD33 and VDD11.

Let me ask you again about f).

Doesn't leakage current occur inside the TUSB7320?

Regards,

Yoda

Yoda:

    XI pin is not  failsafe, if 48MHz is repeatedly applied on XI before VDD11 and VDD33. ESD cell of XI pin could be damaged. So I suggested not longer than 100us before VDD11 and VDD33 is power up.

    for F, leakage current should not occur inside TUSB7320.

   For E, what signal is blue one?

Regards,

brian

Yoda:

    To not damage XI, the earlist 48Mhz clock is 100us from location 2.

   Was there a difference in the recognition of a clock oscillator and a crystal units? Crystal is using internal oscillation circuit and will start working after power is on. clock oscillator could be external clock  and it can be on Xi pin before power is on.

    For 48Mhx CLK enable pin, you can add a cap to delay the signal.

    About "for F, leakage current should not occur inside TUSB7320.", there is no special requirement for peripheral circuit.

Regards,

Brian

Hi Brian：

Please tell us about the "damaged" you are answering.

Does this word mean that the TUSB7320 breaks or doesn't work properly?

Regards,

Yoda