DP83867E: Clock divider on XI pin

Ella KIM

Part Number: DP83867E

Hello there,

Can I get more information on the purpose and selection of CD1 and CD2? It would be appreciated if you can share any relevant material.

Customer supplies a clock into XI pin directly from the output of SG-8101CG with 1.8V level LVCMOS while VDDIO = 1.8V. (that is, they don't implement the clock divider on XI pin) I want to check if this configuration has no issue.

over 4 years ago

0 Nikhil Menon over 4 years ago

TI__Genius 11725 points

Hi Ella,

You are correct, if using VDDIO = 1.8V, no clock divider is required.

Thank you,

Nikhil

All information in this correspondence and in any related correspondence is provided “as is” and “with all faults”, and it is subject to TI’s Important Notice (http://www.ti.com/corp/docs/legal/important-notice.shtml).

0 Ella KIM over 4 years ago in reply to Nikhil Menon

TI__Expert 4212 points

Nikhil,

Thank you for the confirmation. I'd like to know more information on the clock divider circuitry. Could you kindly share any apps note or e2e blog thread dealing with an explanation on the circuitry?

0 Nikhil Menon over 4 years ago in reply to Ella KIM

TI__Genius 11725 points

Hi Ella,

Apologies for the delay. I will be able to provide additional feedback for your query by tomorrow.

Thank you,

Nikhil

+1 Nikhil Menon over 4 years ago in reply to Nikhil Menon

TI__Genius 11725 points

Hi Ella,

The clock divider is used to match the VIH/VIL requirements of each IO level. A different divider is needed for each IO level depending on the level of the clock. Currently, we do not have any additional documentation on this topic. Does this answer your question?

Thank you,

Nikhil

0 Ella KIM over 4 years ago in reply to Nikhil Menon

TI__Expert 4212 points

Thank you, Nikhil!

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DP83867E: Clock divider on XI pin