Hi.
It can now display the same content on both 1920x720 screens,
Not sure how to set the DS90UB941 to support the left and right display to two different 1920 x 720, as shown in the picture above
Could you tell me specifically which registers to set？
Whether to support Pixelclock 74.25x2MHz ?
Hello Gj,
Everything in the script looks correct except for the TSKIP_CNT reg setting. For this video the DSI clock should be 74.25MHz*2*3 = 445MHz, so the TSKIP_CNT reg should be set to 0x30 instead of 0x1E. Also you are missing the init commands from the startup sequence on page 139 of the datasheet:
Those commands need to be added before the last command to enable DSI.
What is the problem you are encountering exactly? Is there no video to either display? If so I would suggest to follow this step by step guide to debug the problem, with the flow chart on page 9: https://www.ti.com/lit/pdf/snla356
Best Regards,
Casey
Hello Casey
WriteI2C (0x40,0x10);
WriteI2C (0x41,0x86);
WriteI2C (0x42,0x0a);
WriteI2C (0x41,0x94);
WriteI2C (0x42,0x0a);
WriteI2C (0x42,0x30)
WriteI2C (0x42,0x0a);
WriteI2C (0x01,0x00); //Enable DSI
The 0x42 register cannot write 5. The 0x42 register cannot write 5. After writing the 0x42 register, read the 0x42 register with a value of 0
add patern ，A screen displays color bars. Nothing else is shown.
add patern:
WriteI2C (0x66,0x03);// # N Div
WriteI2C (0x67,0x23);
WriteI2C (0x66,0x1A); //# M Div
WriteI2C (0x67,0x04);
WriteI2C (0x66,0x04);
WriteI2C (0x67,0x24);
WriteI2C (0x66,0x05);
WriteI2C (0x67,0x98);
WriteI2C (0x66,0x06);
WriteI2C (0x67,0x2D);
WriteI2C (0x66,0x07);
WriteI2C (0x67,0x80);
WriteI2C (0x66,0x08);
WriteI2C (0x67,0x07);
WriteI2C (0x66,0x09);
WriteI2C (0x67,0x2D);
WriteI2C (0x66,0x0A);
WriteI2C (0x67,0x24);
WriteI2C (0x66,0x0B);
WriteI2C (0x67,0x01);
WriteI2C (0x66,0x0C);
WriteI2C (0x67,0x64);
WriteI2C (0x66,0x0D);
WriteI2C (0x67,0x04);
WriteI2C (0x66,0x0E);
WriteI2C (0x67,0x00);
WriteI2C (0x65,0x04);
WriteI2C (0x64,0x05);
Hello gj,
The 0x40-0x42 register sequence is writing to indirect registers within the device. The readback of indirect registers is controlled with bit 0 of the 0x40 registers when you select the indirect page. So with a setting 0x40 = 0x10, then you will be able to write the indirect register, but with a setting of 0x40 = 0x11, then you can read OR write the register.
So from the sound of it, it seems you are able to display PATGEN with internal clock and internal timing so far, but are not able to display the SoC video source?
Please continue with this debug flow chart from the app note I linked before:
So far it looks like you have made it to the red mark. Please continue along this flow chart and let me know where you are getting stuck
Best Regards,
Casey
Hello gj,
The 0x40-0x42 registers sequence is writing to indirect registers within the device. The readback of indirect registers is controlled with bit 0 of the 0x40 registers when you select the indirect page. So with a setting of 0x40 = 0x10 you can write the indirect registers, but with a setting of 0x40 = 0x11 for example you can read OR write the indirect register.
So from the sound of it, it seems you are able to display PATGEN with internal clock and internal timing so far, but are not able to display the SoC video source?
Please continue with this debug flow chart from the app note that I linked before:
So far it looks like you have made it to the red mark. Please continue along this flow chart and let me know where you are getting stuck.
Best Regards,
Casey
