TSB41BA3F-EP: TSB41BA3F-EP IEEE1394b

Francisco Tamez

Part Number: TSB41BA3F-EP
Other Parts Discussed in Thread: TSB82AA2

Hi, I am currently developing a board using 3 - TSB41BA3F-EP devices to receive data from a 3rd party IEEE 1394b simulator equipment. The data from the equipment is received by the PHYs TPA/TPB side (transformer coupled with PULSE TM1062TXHUA), and sent via the D0-D7 interface to an FPGA acting as a LLC device. While doing tests at higher temperature (70C ambient), we noticed that the data on the PHYs parallel bus stops and the STOI bit register on address 0101 is set as well as bus resets been generated. The PCLK signal doesn't seem to stop, only the data. We are trying to understand why this is happening since we cannot find any more information on the datasheet explaining the possible conditions that are setting this bit to stop data flow.

Here are the values of the registers before and after temperature rise

Room Temp			High Temp
PHY1	PHY2	PHY3	PHY1	PHY2	PHY3
c10 - 00006000	1010 - 00006000	1410 - 00006000	c10 - 00006000	1010 - 00006000	1410 - 00006000
c10 - 0000613f	1010 - 0000613f	1410 - 0000613f	c10 - 0000613f	1010 - 0000613f	1410 - 0000613f
c10 - 000062e3	1010 - 000062e3	1410 - 000062e3	c10 - 000062e3	1010 - 000062e3	1410 - 000062e3
c10 - 000063eb	1010 - 000063eb	1410 - 000063eb	c10 - 000063eb	1010 - 000063eb	1410 - 000063eb
c10 - 00006480	1010 - 00006480	1410 - 00006480	c10 - 00006480	1010 - 00006480	1410 - 00006480
c10 - 00006510	1010 - 00006510	1410 - 00006510	c10 - 00006518	1010 - 00006518	1410 - 00006518
c10 - 00006610	1010 - 00006610	1410 - 00006610	c10 - 00006610	1010 - 00006610	1410 - 00006610
c10 - 00006700	1010 - 00006700	1410 - 00006700	c10 - 00006700	1010 - 00006700	1410 - 00006700
c10 - 000068f6	1010 - 000068f6	1410 - 000068f6	c10 - 000068fe	1010 - 000068f6	1410 - 000068fe
c10 - 00006940	1010 - 00006940	1410 - 00006940	c10 - 00006940	1010 - 00006940	1410 - 00006940
c10 - 00006a2a	1010 - 00006a2a	1410 - 00006a2a	c10 - 00006a2a	1010 - 00006a2a	1410 - 00006a2a
c10 - 00006b08	1010 - 00006b08	1410 - 00006b08	c10 - 00006b08	1010 - 00006b08	1410 - 00006b08
c10 - 00006c0e	1010 - 00006c1f	1410 - 00006c11	c10 - 00006c02	1010 - 00006c03	1410 - 00006c02
c10 - 00006d00	1010 - 00006d00	1410 - 00006d00	c10 - 00006d00	1010 - 00006d00	1410 - 00006d00
c10 - 00006e00	1010 - 00006e00	1410 - 00006e00	c10 - 00006e00	1010 - 00006e00	1410 - 00006e00
c10 - 00006f1d	1010 - 00006f1d	1410 - 00006f1d	c10 - 00006f1d	1010 - 00006f1d	1410 - 00006f1d

The current setup we are using for the Port Speed / Mode selections is MODE1 as shown on Table 5-1 on the datasheet.

I can provide a schematic if needed to check the pinout setting.

Thanks for the help with this issue.

Francisco

over 2 years ago

0 David (ASIC) Liu over 2 years ago

TI__Guru*** 140145 points

Francisco

Can you probe the LPS? Are you seeing the LPS from the FPGA going low?

Thanks

David

0 Francisco Tamez over 2 years ago

Prodigy 60 points

Hi David,

Initially we had the LPS tied high and after reviewing the datasheet and comparing it to the schematic connection we have (10K pull-down) we noticed that it requires a square-Wave Input (Figure 13-6 Nonisolated Connection Variations for LPS, page 60), so we generated a 2MHz pulse on the LPS signal to the PHYs to emulate the functionality of the LLC TSB82AA2, which we had used before on another design in an effort to solve the problem. However, we didn't notice a difference on the STOI register. Should we hold it low instead?

From the LLC datasheet

Thanks

Francisco

0 David (ASIC) Liu over 2 years ago in reply to Francisco Tamez

TI__Guru*** 140145 points

Francisco

LPS is used to indicate the powered status of the link to the PHY and is also used to indicate that the PHY is to reset, disable,
or enable the PHY-link interface.

It must be connected to either the VDD supplying the LLC through an approximately 1-kΩ resistor or to a pulsed output which is active when the LLC is powered. A pulsed signal must be used when an isolation barrier exists between the LLC and PHY.

When testing at 70C and when the PHY STOI bit is set, are you seeing any change on the LPS signal?

Thanks

David

0 Francisco Tamez over 2 years ago in reply to Francisco Tamez

Prodigy 60 points

Hi David,

We are going to do the test again at 70C and monitor the LPS signal. I'll let you know what we see.

Thanks

Francisco

0 David (ASIC) Liu over 2 years ago in reply to Francisco Tamez

TI__Guru*** 140145 points

Francisco

When you had LPS tied high permanently, did you ever see the PHY STOI bit getting set when testing at 70C?

Thanks

David

0 Francisco Tamez over 2 years ago in reply to David (ASIC) Liu

Prodigy 60 points

Hi David,

When we had the LPS high the STOI register was set. The temperature chamber is still in use, so we haven't had a chance to do the test.

Thanks

Francisco

0 David (ASIC) Liu over 2 years ago in reply to Francisco Tamez

TI__Guru*** 140145 points

Francisco

Thanks, I will wait for your test result.

David

0 Francisco Tamez over 2 years ago in reply to David (ASIC) Liu

Prodigy 60 points

Hi David, it seems the problems was created by some timing issue on the FPGA. The STOI was never set while the LPS was active. We are going to test another unit and verify if that is tin fact the issue before we close this case. I'll keep you posted with the results.

Thanks

Francisco

0 Francisco Tamez over 2 years ago in reply to Francisco Tamez

Prodigy 60 points

Hi David, we are going to test another unit soon to verify if the issue was related to the FPGA. I'll let you know the results to close the blog.

Thanks

Francisco

0 David (ASIC) Liu over 2 years ago in reply to Francisco Tamez

TI__Guru*** 140145 points

Francisco

Sounds good, thanks for the continuing update.

Thanks

David

+1 Francisco Tamez over 2 years ago

Prodigy 60 points

HI David,

We finally tested 2 more units and the issue was on the FPGA side. Sorry for the delayed response. Thanks for your help with this.

Interface

Interface forum

TSB41BA3F-EP: TSB41BA3F-EP IEEE1394b