TCAN4551-Q1: Is there a difference between the MCAN interrupt registers at 0x0824 and 0x1050?

Part Number: TCAN4551-Q1

It's not clear to me from the data sheet if there is a difference between the register at 0x0824 and the one at 0x1050?

I'm struggling with efficiency of the example code, and was wondering if I could read 0x8020 and 0x0824 at the same time, instead of reading 0x8020 and 0x1050 separately.

The data sheet is confusing as it sometimes uses only names, acronyms, or hex addresses, and the register maps/tables are only provided for the MCAN section.

Thanks in advance, 


  • Hi Ed,

    The 0x0824 register mirrors the state of the 0x1050 register. This is done so that an extended read of 0x0820 and 0x0824 may be done to get all interrupt data quickly, as it sounds like is the goal here. To clear the MCAN interrupts, writes must be done to the 0x1050 register, as writes to the mirror register are not allowed. Similarly, the MCAN interrupt enable register is only in the 0x10xx memory space. 

    I'm surprised that this is not stated explicitly in the datasheet and I agree a statement on this in the document would be helpful for understanding the intended use case. I'll keep this in mind for future revisions. 

    Let me know if you have any more questions.

    Eric Schott