The datasheet for DP83848 indicates in Table 3-4, that the pin XI expects a 25MHz external clock source in MII Mode.
Further, the Functional Block Diagram in Section 1.4 depicts a "Clock Generation" block and a 25MHz Clock Source for both 10/100Mbps.
The assumption that I am making from this is that in 100Mbps-MII Mode, the PHY essentially sends the 25MHz Clock Input as TX_CLK and RX_CLK to the EMAC. In 10Mbps-MII Mode, the PHY has a frequency divider (/10) to generate TX_CLK and RX_CLK of 2.5MHz from the same 25MHz Clock Input. This frequency divider operation seems to be reflected by Bits 11-15 in BMSR (Basic Mode Status Register).
Is the above assumption (of generating 2.5MHz or 25MHz from same 25MHz clock source) correct ? If yes, is there any documentation of this frequency divider and/or some system description of the frequency divider outputs being controlled by Strap Option Pins (AN_EN, AN_1, AN_0 and MII_MODE) ?
