Hello,
My customer has a problem with connecting a TCAN4550 with their FPGA. I think It could be software problem because it happen also with our EVM. See his description below.
Thanks
Jan
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We would like the use the TCAN 4550 on the development board (TCAN4550 evaluation module) with the following CANFD setup:
Please find the SPI transactions at the end of this message.
N 1MBit
N SP 80%
N Prescaler: 4
N seq1: 7
N Seq2: 2
N SJW: 2
N 10Tq
D 8MBit
D SP 60%
D Prescaler: 1
D seq1: 2
D Seq2: 2
D SJW: 2
D 5 Tq
Watchdog not required
Sleep not required
GPIs, GPOs, IRQs not required
Only one TX buffer is configured for sending a message to the CAN bus.
Receiving of messages is not required at the moment.
Problem:
========
After sending SPI transaction "Init 8", the status LEDs on the development board light up.
Only the SPI transactions "Verify_Read_Init 0" to "Verify_Read_Init 1" provide readback data. Then MISO remains silent.
A power cycle of the development board is required in order to get another response on MISO.
Two Master devices show similar behavior with the given set of SPI transactions.
Could you please have a look at our SPI transactions?
It seems, there is an error in the configuration.
The following procedure is implemented:
=======================================
1.
The master sends initialization.
SPI transactions: "Reset 0" and "Init 0" to "Init 8"
2.
Some of the initialization is read back and checked
SPI transactions: "Read_Init 0" to "Read_Init 6"
Expected readback data: "Verify_Read_Init 0" to "Verify_Read_Init 6"
If readback data is go then goto 3.
else goto 2.
3.
Check if a new message can be loaded to the TX buffer
SPI transaction: "CheckCanBuffer 0"
If the buffer is ready for new data then goto 4.
else goto 2.
4.
Load message and request to send
SPI transactions "Writing64B 0" to "Writing64B 1"
goto 2.
SPI transactions and expected readback:
======================================
Initialization:
Reset 0 ['0x61', '0x8', '0x0', '0x1', '0xc8', '0x0', '0x4', '0x6c']
Init 0 ['0x61', '0x10', '0x18', '0x1', '0x0', '0x0', '0x83', '0x43']
Init 1 ['0x61', '0x10', '0x1c', '0x1', '0x2', '0x3', '0x6', '0x1']
Init 2 ['0x61', '0x10', '0xc', '0x1', '0x0', '0x80', '0x1', '0x11']
Init 3 ['0x61', '0x10', '0x48', '0x1', '0x0', '0x0', '0x4', '0x0']
Init 4 ['0x61', '0x10', '0xc0', '0x1', '0x1', '0x0', '0x0', '0x0']
Init 5 ['0x61', '0x10', '0xc8', '0x1', '0x0', '0x0', '0x0', '0x7']
Init 6 ['0x61', '0x80', '0x0', '0x2', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0']
Init 7 ['0x61', '0x10', '0x18', '0x1', '0x0', '0x0', '0x83', '0x40']
Init 8 ['0x61', '0x8', '0x0', '0x1', '0x38', '0x0', '0x6', '0xa2']
Readback of some initialization:
Read_Init 0 ['0x41', '0x10', '0x1c', '0x1', '0xff', '0xff', '0xff', '0xff']
Read_Init 1 ['0x41', '0x10', '0xc', '0x1', '0xff', '0xff', '0xff', '0xff']
Read_Init 2 ['0x41', '0x10', '0x48', '0x1', '0xff', '0xff', '0xff', '0xff']
Read_Init 3 ['0x41', '0x10', '0xc0', '0x1', '0xff', '0xff', '0xff', '0xff']
Read_Init 4 ['0x41', '0x10', '0xc8', '0x1', '0xff', '0xff', '0xff', '0xff']
Read_Init 5 ['0x41', '0x10', '0x18', '0x1', '0xff', '0xff', '0xff', '0xff']
Read_Init 6 ['0x41', '0x8', '0x0', '0x1', '0xff', '0xff', '0xff', '0xff']
expected readback data:
Verify_Read_Init 0 ['0x0', '0x0', '0x0', '0x0', '0x02', '0x03', '0x06', '0x01']
Verify_Read_Init 1 ['0x0', '0x0', '0x0', '0x0', '0x00', '0x80', '0x01', '0x11']
Verify_Read_Init 2 ['0x0', '0x0', '0x0', '0x0', '0x00', '0x00', '0x04', '0x00']
Verify_Read_Init 3 ['0x0', '0x0', '0x0', '0x0', '0x01', '0x00', '0x00', '0x00']
Verify_Read_Init 4 ['0x0', '0x0', '0x0', '0x0', '0x00', '0x00', '0x00', '0x07']
Verify_Read_Init 5 ['0x0', '0x0', '0x0', '0x0', '0x00', '0x00', '0x83', '0x40']
Verify_Read_Init 6 ['0x0', '0x0', '0x0', '0x0', '0x38', '0x00', '0x06', '0xa2 (only some of the bits)']
Check if a new message can be loaded to the TX buffer:
CheckCanBuffer 0 ['0x41', '0x10', '0xc4', '0x1', '0xff', '0xff', '0xff', '0xff']
Loading a CAN message and request to send:
Writing64B 0 ['0x61', '0x80', '0x0', '0x12', '0x5a', '0xaa', '0xaa', '0xaa', '0x1', '0x3f', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0', '0x0']
Writing64B 1 ['0x61', '0x10', '0xd0', '0x1', '0x0', '0x0', '0x0', '0x1']
