• State
  • Locked Locked
  • Replies 5 replies
  • Subscribers 33 subscribers
  • Views 1137 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83620 and PTP Synchronization

Bob Ledoux
Prodigy 130 points
Other Parts Discussed in Thread: DP83620, DP83640, DP83630

Hello, I would like to use the DP83620 and PTP for a physical layer application only (No MAC IP layer stack). To use the SYNC Eth feature, does the DP83620 need to see certain IP1588  packets to achieve synchronization with a remote slave device? Or can the DP83620 sync up on its own?

I am referencing SNLA100A (AN-1730), page 4, paragraph 3. "When SYNCE mode is enabled, control of the PTP clock, digital counter, and PTP rate adjust logic is switched to the recovered receive clock. This has the effect of locking the PTP clock and counter of the slave system to the PTP clock and counter of the master system."

I also notice that the DP83620 does not provide the PTP 1588 BASE REGISTERS like the DP83640 does.

In my application I am just using the Ethernet Physical layer (no IP stack). ideally I would like to have SYNCe automatically sync the master to slave without having to implement the 1588 protocol.  It looks like the DP83620 is what I am looking for.

Regards,

Bob Ledoux

Edgetech

  • 0
    TI__Mastermind 31600 points
    When setting SYNC_ENET EN, bit 13 in the PHY Control Register 2 (PHYCR2), Address 0x1C, the clock that is recovered from the receive signaling will be used to synchronize the transmitter (i.e. the line driver). This clock can also be brought out on the CLK_OUT pin.

    No IEEE 1588 packets are required for this functionality. The DP83620 does not provide support for IEEE 1588. For IEEE 1588 support, you would need to use the DP83640 or the DP83630.

    Patrick
  • 0 in reply to Patrick OFarrell
    Prodigy 130 points

    Thank You for the feedback Patrick.

    So once the slave receiver, transmitter and CLK_OUT pin are synchronized to master transmitter; the slave clock will be phase locked and track the master clock. Is that correct?

    Regards,

    Bob Ledoux

  • 0 in reply to Bob Ledoux
    TI__Mastermind 31600 points
    Bob,

    Yes, the slave clock will lock to the master clock and will track that frequency. Note that the expectations for the reference clock drift still hold. That is to say, the master clock should still be within the +/-50ppm range.

    Patrick
  • 0 in reply to Patrick OFarrell
    Prodigy 130 points

    Patrick, Table 1 of the SNLA100A (AN-1730) app-note shows the Master Reference Clock using an OCXO which is much better than +/-50ppm. Is it true, I can use a lower grade oscillator around 50ppm and SYNCe will still work?

    Is the DP83620 recommended for new designs?

    Is it possible to obtain the DP83620 demo boards as a loaner? Ideally, I would like to test the concept before building prototypes, I feel that $399 per demo board is steep for a one-time SYNCe test.

    Hello Patrick, I have also attached a doc file with additional questions.

    SYNCe support.docxRegards,
    Bob

  • 0 in reply to Bob Ledoux
    Prodigy 130 points
    Hello, please help and respond to the technical questions I posed above in the thread. I would like to design in the DP83620 but I need to learn more about the SYNCe capability.