[FAQ] DS280DF810: What are register settings to enable prbs generator and checker using a simple divide by 2, 4, or 8 clock

Enabling PRBS Generator/Checker Through Register Setting:
The followings are register settings to enable 25Gbps PRBS31 generator on channel 0 and PRBS31 checker on channel 1.

Note prior to issuing these register settings, make sure we have the following hardware setup:
1). Turn off output of the clock generator and connect divide by 2,4, or 8 clock to RXP0/RXN0 - using 100-ohm SMA cable
2). Connect - using differential 100-ohm SMA cable - to TXP0/TXN0 to RXP1/RXN1
3). Turn power on to the device under test
4). Turn on output of the clock generator
RAW FF 03 33 //select channel register and broadcast to all channels
RAW FC 01 FF //select register set for channel 0
RAW 2F 40 F0 //**setup every channel to lock to 25gbps
RAW 60 80 FF //setup device channel 0 and other channels to lock to 25gbps
RAW 61 BE FF
RAW 62 80 FF
RAW 63 BE FF
RAW 64 FF FF
RAW 09 04 04 //divider override
RAW 18 00 70 //divide by 1 since we want to generate highest rate
RAW 0A 0C 0C //assert cdr reset
RAW 0A 00 0C //release CDR reset
RAW FF 01 33 //**enable channel 0 only to generate prbs31
RAW FC 01 01 //this may not be needed since we already did this earlier
RAW 2E 04 04 //allow selection of prbs31
RAW 30 01 03 //enable prbs31
RAW 1E 10 10 //turn on prbs generator serializer
RAW 79 00 20 //toggle prbs_gen_en
RAW 79 20 20
RAW 30 00 08 //toggle prbs digital clock
RAW 30 08 08
RAW A5 80 E0 //select prbs generator on output mux
RAW FF 01 33 //**check to make sure channel 0 is locked to 25Gbps from channel
RAW FC 01 FF //select register set for channel 0
RAW 78 00 00 //check bit 4 if set lock is detected
RAW FF 01 33 //**enable channel register & don’t broadcast
RAW FC 02 FF //select register set for channel 1
RAW 78 00 00 //bits 5 and 4 must be set (sig detect and lock asserted)
RAW 0D 00 80 //turn on prbs de-serializer for channel 1
RAW 79 40 40 //enable prbs checker
RAW 30 00 08 //toggle digital clock
RAW 30 08 08
RAW 30 10 10 //force reload of prbs checker seed
RAW 30 00 10
RAW 82 40 40 //reset prbs counters
RAW 82 00 40
RAW 01 00 00 //check 0x01[6] if set polarity inverted else interverted
RAW 01 00 00 //check 0x01[4] if set prbs pattern detected
RAW 01 00 00 //check 0x01[3:0] if equal to 3'b101 prbs31 detected
RAW 82 80 80 //** check prbs31 error count freeze the current error counter
RAW 83 00 00 //0x83[2:0] is msb for error count[10:8]
RAW 84 00 00 //0x84[7:0] is lsb for error count[7:0]
RAW 82 00 80 //un-freeze prbs error count