DS90UB935-Q1: Review the schematic and the registre settings

Nao

Genius 4905 points

Part Number: DS90UB935-Q1

Hello, E2E members

Can you help to review the schematic and the register settings as attachment?

DS90UB935_934_936_Setting_20190603_r1p0a.pdf

Regards,
Nao

over 6 years ago

0 Jiashow Ho over 6 years ago

TI__Genius 11340 points

Hi Nao,

The block diagrams and register setting look good.

My only comment is that is DVP_CFG necessary (for 935/934)? What are you sending in DVP_DT_MAT_CH_VAL? If you are actually using that register, then this should be fine.

Best,

Jiashow

0 Nao over 6 years ago in reply to Jiashow Ho

Genius 4905 points

Hello, Jiashow

Thank you for your quick feedback.

What is the DVP_DT_MAT_CH_VAL (register or bit?)?
I can't find it in DS90UB934/935 datasheet.

Regards,
Nao

0 Jiashow Ho over 6 years ago in reply to Nao

TI__Genius 11340 points

Hi Nao,

When you have reg 0x10[3] = b'1, the DVP block will allow packets with the DT from 0x11[5:0] (DVP_DT_MATCH_VAL) to go through regardless of the mode_75m or mode_100m setting. It doesn't seem like you are using it so you can simply set 0x10[3] = b'0.

Best,

Jiashow

0 Nao over 6 years ago in reply to Jiashow Ho

Genius 4905 points

Hello, Jiashow

Thank you for your feedback.
However, We dose not set 0x10[3] = b'1.
Our customer's setting is 0x10 (DVP_CFG) = 0x10(0x10[4] = b'1).
If there are any mistakes in my understanding please let me know.

Regards,
Nao

0 Jiashow Ho over 6 years ago in reply to Nao

TI__Genius 11340 points

Hi Nao,

My apology, I misread the register, please disregard what I said earlier about 0x10[3].

Setting 0x10[4] will allow any packets with DT to be pass through. If this is the intent it's fine.

Best,

Jiashow

0 Nao over 6 years ago in reply to Jiashow Ho

Genius 4905 points

Hello, Jiashow

Thnak you for your quick reply.

I forgot to check the one register setting too.
It are CLKOU_CTRLx.

I asked this register settings at other E2E.
https://e2e.ti.com/support/interface/f/138/t/800345

This register sets same vaule, isn't it?
0x06=0x41
0x07=0x0E

Regards,
Nao

0 Nao over 6 years ago in reply to Nao

Genius 4905 points

Hello, Jiashow

Do you have any update?

Regards,

Nao

0 Jiashow Ho over 6 years ago in reply to Nao

TI__Genius 11340 points

Hi Nao,

For 935-934 RAW10 mode:

Line Rate = PCLK * 28 = 96 * 28 = 2.69Gbps

With reg 0x06 = 0x41 and 0x07 = 0x1C, you get a 24.0MHz CLKOUT

For 935-936 Sync mode:

Line Rate = 4G

If you want 24MHz clock, you need 0x06 = 0x43 and 0x07 = 0x7D.

If you want M/N integer, you can set to 23.8MHz clock by setting 0x06= 0x41 and 0x07 = 0x2A.

Best,

Jiashow

0 Nao over 6 years ago in reply to Jiashow Ho

Genius 4905 points

Hi, Jiashow

Thank you for your reply.

I have one more simple question.
Datasheet said that " (1) HS_CLK_DIV typically should be set to either 16 ,8 or 4.".
Can we set the divide 2 or 1 setting on HS_CLK_DIV bits?

Regards,
Nao

0 Jiashow Ho over 6 years ago in reply to Nao

TI__Genius 11340 points

Hi Nao,

Yes. You can set HS_CLK_DIV to 2 or 1.

Best,

Jiashow

0 Nao over 6 years ago in reply to Jiashow Ho

Genius 4905 points

Hi, Jiashow

Thank you for your quick feedback.
I will send your comment to my customer.
I can close this thread, if our customer dose not have more questions.

Could you wait until this weekend for that?

Regards,
Nao

0 Jiashow Ho over 6 years ago in reply to Nao

TI__Genius 11340 points

Should be fine! Thanks, Nao.

Best,

Jiashow

0 Nao over 6 years ago in reply to Jiashow Ho

Genius 4905 points

Hi, Jiashow

Our customer does not have more questions.
I can close this thread.

Regards,
Nao

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DS90UB935-Q1: Review the schematic and the registre settings