Other Parts Discussed in Thread: ALP
Hello TI,
I am struggling to display the MIPI CSI-2 image from the 954-Q1EVM / 953-EVM kits. After probing, I do not see the reference clock 25 MHz active from your 954-Q1EVM. How do I make the Ref CLK active? I am sending the POC voltages and the Pass and Lock LED's are lit on the 954-Q1EVM.
I am using a Cypress CX3 Denebola RDK eval board with a custom adapter board to link the differential CSI data lines, CLK lines, and I2C lines between the CX3 and your 954-Q1EVM.
Below is my status after running the following Python scripts ( 954_script_A1_RX0_init_CSI0_broadcast.py and ovt_1280_1080_30fps_REMOTE_RevE2_ID7a.py). Please help provide any additional Python code I need to run to ensure the link is proper. Can you send me the Python Scripts to my email? emilio.cuesta@te.com
My concerns are listed below:
-REF CLK not seen from the J24 connector
- "Current CSI TX Status" Port 0 Sync Status shows "No" , but the Pass Status displays "Pass". Maybe the REF CLK not being seen can be a cause.
Thank you for your assistance!